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Message-ID: <20190920132644.GA226476@google.com>
Date:   Fri, 20 Sep 2019 08:26:44 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Kai-Heng Feng <kai.heng.feng@...onical.com>
Cc:     tiwai@...e.com, Linux PCI <linux-pci@...r.kernel.org>,
        alsa-devel@...a-project.org, LKML <linux-kernel@...r.kernel.org>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>
Subject: Re: [PATCH 1/2] PCI: Add a helper to check Power Resource
 Requirements _PR3 existence

[+cc Rafael]

On Fri, Sep 20, 2019 at 01:23:20PM +0200, Kai-Heng Feng wrote:
> On Mon, Sep 9, 2019 at 1:41 PM Bjorn Helgaas <helgaas@...nel.org> wrote:

> > > +bool pci_pr3_present(struct pci_dev *pdev)
> > > +{
> > > +     struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
> > > +     struct acpi_device *parent_adev;
> > > +
> > > +     if (acpi_disabled)
> > > +             return false;
> > > +
> > > +     if (!parent_pdev)
> > > +             return false;
> > > +
> > > +     parent_adev = ACPI_COMPANION(&parent_pdev->dev);
> > > +     if (!parent_adev)
> > > +             return false;
> > > +
> > > +     return parent_adev->power.flags.power_resources &&
> > > +             acpi_has_method(parent_adev->handle, "_PR3");
> >
> > I think this is generally OK, but it doesn't actually check whether
> > *pdev* has a _PR3; it checks whether pdev's *parent* does.  So does
> > that mean this is dependent on the GPU topology, i.e., does it assume
> > that there is an upstream bridge and that power for everything under
> > that bridge can be managed together?
> 
> Yes, the power resource is managed by its upstream port.
> 
> > I'm wondering whether the "parent_pdev = pci_upstream_bridge()" part
> > should be in the caller rather than in pci_pr3_present()?
> 
> This will make the function more align to its name, but needs more
> work from caller side.
> How about rename the function to pci_upstream_pr3_present()?

I cc'd Rafael because he knows all about how this stuff works, and I
don't.

_PR3 is defined in terms of the device itself and the doc (ACPI v6.3,
sec 7.3.11) doesn't mention any hierarchy.  I assume it would be legal
for firmware to supply a _PR3 for "pdev" as well as for "parent_pdev"?

If that is legal, I think it would be appropriate for the caller to
look up the upstream bridge.  That way this interface could be used
for both "pdev" and an upstream bridge.  If we look up the bridge
internally, we would have to add a second interface if we actually
want to know about _PR3 for the device itself.

> > I can't connect any of the dots from _PR3 through to
> > "need_eld_notify_link" (whatever "eld" is :)) and the uses of
> > hda_intel.need_eld_notify_link (and needs_eld_notify_link()).
> >
> > But that's beyond the scope of *this* patch and it makes sense that
> > you do want to discover the _PR3 existence, so I'm fine with this once
> > we figure out the pdev vs parent question.
> 
> Thanks for your review.
> 
> Kai-Heng
> 
> >
> > > +}
> > > +EXPORT_SYMBOL_GPL(pci_pr3_present);
> > > +
> > >  /**
> > >   * pci_add_dma_alias - Add a DMA devfn alias for a device
> > >   * @dev: the PCI device for which alias is added
> > > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > > index 82e4cd1b7ac3..9b6f7b67fac9 100644
> > > --- a/include/linux/pci.h
> > > +++ b/include/linux/pci.h
> > > @@ -2348,9 +2348,11 @@ struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
> > >
> > >  void
> > >  pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
> > > +bool pci_pr3_present(struct pci_dev *pdev);
> > >  #else
> > >  static inline struct irq_domain *
> > >  pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
> > > +static bool pci_pr3_present(struct pci_dev *pdev) { return false; }
> > >  #endif
> > >
> > >  #ifdef CONFIG_EEH
> > > --
> > > 2.17.1
> > >

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