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Message-Id: <20190921151223.768842-2-martin.blumenstingl@googlemail.com>
Date: Sat, 21 Sep 2019 17:12:19 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: narmstrong@...libre.com, jbrunet@...libre.com, robh+dt@...nel.org,
mark.rutland@....com, linux-amlogic@...ts.infradead.org,
devicetree@...r.kernel.org, khilman@...libre.com
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: [PATCH 1/5] dt-bindings: clock: meson8b: add the clock inputs
The clock controller on Meson8/Meson8b/Meson8m2 has three (known)
inputs:
- "xtal": the main 24MHz crystal
- "ddr_pll": some of the audio clocks use the output of the DDR PLL as
input
- "clk_32k": an optional clock signal which can be connected to GPIOAO_6
(which then has to be switched to the CLK_32K_IN function)
Add the inputs to the documentation so we can wire up these inputs in a
follow-up patch.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
---
.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 4d94091c1d2d..cc51e4746b3b 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -11,6 +11,11 @@ Required Properties:
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
- #clock-cells: should be 1.
- #reset-cells: should be 1.
+- clocks: list of clock phandles, one for each entry in clock-names
+- clock-names: should contain the following:
+ * "xtal": the 24MHz system oscillator
+ * "ddr_pll": the DDR PLL clock
+ * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
Parent node should have the following properties :
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
--
2.23.0
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