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Message-ID: <1jwodzs6ir.fsf@starbuckisacylon.baylibre.com>
Date: Mon, 23 Sep 2019 11:31:40 +0200
From: Jerome Brunet <jbrunet@...libre.com>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
narmstrong@...libre.com, robh+dt@...nel.org, mark.rutland@....com,
linux-amlogic@...ts.infradead.org, devicetree@...r.kernel.org,
khilman@...libre.com
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: Re: [PATCH 4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF
On Sat 21 Sep 2019 at 17:12, Martin Blumenstingl <martin.blumenstingl@...glemail.com> wrote:
> The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock
> driver should not register the XTAL clock - instead it should be
> provided via .dts and then passed to the clock controller.
>
> Skip the registration of the XTAL clock if a parent clock is provided
> via OF. Fall back to registering the XTAL clock if this is not the case
> to keep support for old .dtbs.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> ---
> drivers/clk/meson/meson8b.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index b785b67baf2b..15ec14fde2a0 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -3682,10 +3682,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
> meson8b_clk_regmaps[i]->map = map;
>
> /*
> - * register all clks
> - * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
> + * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
> + * XTAL clock as input.
> */
> - for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
> + if (of_clk_get_parent_count(np))
If we are going for this, I'd prefer if could explicity check for the
clock named "xtal" instead of just checking if DT has clocks.
> + i = CLKID_PLL_FIXED;
> + else
> + i = CLKID_XTAL;
> +
> + /* register all clks */
> + for (; i < CLK_NR_CLKS; i++) {
> /* array might be sparse */
> if (!clk_hw_onecell_data->hws[i])
> continue;
> --
> 2.23.0
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