linux-kernel - Re: [PATCH v22 02/24] x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20190925172815.GG3891@zn.tnic>
Date:   Wed, 25 Sep 2019 19:28:15 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Sean Christopherson <sean.j.christopherson@...el.com>
Cc:     Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>,
        linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-sgx@...r.kernel.org, akpm@...ux-foundation.org,
        dave.hansen@...el.com, nhorman@...hat.com, npmccallum@...hat.com,
        serge.ayoun@...el.com, shay.katz-zamir@...el.com,
        haitao.huang@...el.com, andriy.shevchenko@...ux.intel.com,
        tglx@...utronix.de, kai.svahn@...el.com, josh@...htriplett.org,
        luto@...nel.org, kai.huang@...el.com, rientjes@...gle.com,
        cedric.xing@...el.com, Kai Huang <kai.huang@...ux.intel.com>,
        Haim Cohen <haim.cohen@...el.com>
Subject: Re: [PATCH v22 02/24] x86/cpufeatures: x86/msr: Intel SGX Launch
 Control hardware bits

On Wed, Sep 25, 2019 at 09:49:32AM -0700, Sean Christopherson wrote:
> Correct, only X86_FEATURE_SGX_LC is cleared.  The idea is to have SGX_LC
> reflect whether or not flexible launch control is fully enabled, no more
> no less.

So we do not disable SGX when the MSRs are read-only - we disable only
launch control.

> Functionally, this doesn't impact support for native enclaves as the
> driver will refuse to load if SGX_LC=0.

So why aren't we clearing all feature bits then? What's the purpose for
leaving them set if we're not going to support hardcoded OEM vendor hash
in the MSRs anyway?

> Looking forward, this *will* affect KVM.  As proposed, KVM would expose
> SGX to a guest regardless of SGX_LC support.
> 
> https://lkml.kernel.org/r/20190727055214.9282-17-sean.j.christopherson@intel.com

... which would do what exactly? Guests can execute SGX only
when signed by the Intel key, when LC is disabled?

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette