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Message-ID: <CAERHkrs4=pgG-+Bd=YLzZ2RWEPTDX0x70Zb4haTwSZODyC2NLw@mail.gmail.com>
Date:   Thu, 26 Sep 2019 06:07:42 +0800
From:   Aubrey Li <aubrey.intel@...il.com>
To:     Tim Chen <tim.c.chen@...ux.intel.com>
Cc:     Dario Faggioli <dfaggioli@...e.com>,
        Julien Desfossez <jdesfossez@...italocean.com>,
        "Li, Aubrey" <aubrey.li@...ux.intel.com>,
        Aaron Lu <aaron.lu@...ux.alibaba.com>,
        Subhra Mazumdar <subhra.mazumdar@...cle.com>,
        Vineeth Remanan Pillai <vpillai@...italocean.com>,
        Nishanth Aravamudan <naravamudan@...italocean.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Paul Turner <pjt@...gle.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Linux List Kernel Mailing <linux-kernel@...r.kernel.org>,
        Frédéric Weisbecker <fweisbec@...il.com>,
        Kees Cook <keescook@...omium.org>,
        Greg Kerr <kerrnel@...gle.com>, Phil Auld <pauld@...hat.com>,
        Valentin Schneider <valentin.schneider@....com>,
        Mel Gorman <mgorman@...hsingularity.net>,
        Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
        Paolo Bonzini <pbonzini@...hat.com>
Subject: Re: [RFC PATCH v3 00/16] Core scheduling v3

On Thu, Sep 26, 2019 at 1:24 AM Tim Chen <tim.c.chen@...ux.intel.com> wrote:
>
> On 9/24/19 7:40 PM, Aubrey Li wrote:
> > On Sat, Sep 7, 2019 at 2:30 AM Tim Chen <tim.c.chen@...ux.intel.com> wrote:
> >> +static inline s64 core_sched_imbalance_delta(int src_cpu, int dst_cpu,
> >> +                       int src_sibling, int dst_sibling,
> >> +                       struct task_group *tg, u64 task_load)
> >> +{
> >> +       struct sched_entity *se, *se_sibling, *dst_se, *dst_se_sibling;
> >> +       s64 excess, deficit, old_mismatch, new_mismatch;
> >> +
> >> +       if (src_cpu == dst_cpu)
> >> +               return -1;
> >> +
> >> +       /* XXX SMT4 will require additional logic */
> >> +
> >> +       se = tg->se[src_cpu];
> >> +       se_sibling = tg->se[src_sibling];
> >> +
> >> +       excess = se->avg.load_avg - se_sibling->avg.load_avg;
> >> +       if (src_sibling == dst_cpu) {
> >> +               old_mismatch = abs(excess);
> >> +               new_mismatch = abs(excess - 2*task_load);
> >> +               return old_mismatch - new_mismatch;
> >> +       }
> >> +
> >> +       dst_se = tg->se[dst_cpu];
> >> +       dst_se_sibling = tg->se[dst_sibling];
> >> +       deficit = dst_se->avg.load_avg - dst_se_sibling->avg.load_avg;
> >> +
> >> +       old_mismatch = abs(excess) + abs(deficit);
> >> +       new_mismatch = abs(excess - (s64) task_load) +
> >> +                      abs(deficit + (s64) task_load);
> >
> > If I understood correctly, these formulas made an assumption that the task
> > being moved to the destination is matched the destination's core cookie.
>
> That's not the case.  We do not need to match the destination's core cookie,

I actually meant destination core's core cookie.

> as that may change after context switches. It needs to reduce the load mismatch
> with the destination CPU's sibling for that cgroup.

So the new_mismatch is not always true, especially when there are more
cgroups and
more core cookies on the system.

Thanks,
-Aubrey

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