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Message-ID: <20190927103420.48bb9335@windsurf>
Date: Fri, 27 Sep 2019 10:34:20 +0200
From: Thomas Petazzoni <thomas.petazzoni@...tlin.com>
To: Remi Pommarel <repk@...plefau.lt>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] PCI: aardvark: Don't rely on jiffies while holding
spinlock
Hello Remi,
Thanks for the new iteration!
On Fri, 27 Sep 2019 10:31:42 +0200
Remi Pommarel <repk@...plefau.lt> wrote:
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index fc0fe4d4de49..ee05ccb2b686 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -175,7 +175,8 @@
> (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
> PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
>
> -#define PIO_TIMEOUT_MS 1
> +#define PIO_RETRY_CNT 10
> +#define PIO_RETRY_DELAY 2 /* 2 us*/
So this changes the timeout from 1ms to just 20us, a division by 50
from the previous timeout value. From my measurements, it could
sometime take up to 6us from a single PIO read operation to complete,
which is getting close to the 20us timeout.
Shouldn't PIO_RETRY_CNT be kept at 500, so that we keep using a 1ms
timeout ?
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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