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Message-ID: <20190930221416.GA2501@bogus>
Date: Mon, 30 Sep 2019 17:14:16 -0500
From: Rob Herring <robh@...nel.org>
To: Lina Iyer <ilina@...eaurora.org>
Cc: swboyd@...omium.org, evgreen@...omium.org, maz@...nel.org,
linus.walleij@...aro.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, bjorn.andersson@...aro.org,
mkshah@...eaurora.org, linux-gpio@...r.kernel.org,
Lina Iyer <ilina@...eaurora.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH RFC v2 06/14] dt-bindings/interrupt-controller: pdc: add
SPI config register
On Fri, 13 Sep 2019 15:59:14 -0600, Lina Iyer wrote:
> In addition to configuring the PDC, additional registers that interface
> the GIC have to be configured to match the GPIO type. The registers on
> some QCOM SoCs are access restricted, while on other SoCs are not. They
> SoCs with access restriction to these SPI registers need to be written
> from the firmware using the SCM interface. Add a flag to indicate if the
> register is to be written using SCM interface.
>
> Cc: devicetree@...r.kernel.org
> Signed-off-by: Lina Iyer <ilina@...eaurora.org>
> ---
> .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@...nel.org>
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