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Message-ID: <20190930230806.2940505-35-paul.burton@mips.com>
Date: Mon, 30 Sep 2019 23:08:44 +0000
From: Paul Burton <paul.burton@...s.com>
To: "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>
CC: Huacai Chen <chenhc@...ote.com>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Paul Burton <pburton@...ecomp.com>
Subject: [PATCH 34/37] MIPS: barrier: Make __smp_mb__before_atomic() a no-op
for Loongson3
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
emit a full completion barrier as part of the inline assembly containing
LL/SC loops for atomic operations. As such the barrier emitted by
__smp_mb__before_atomic() is redundant, and we can remove it.
Signed-off-by: Paul Burton <paul.burton@...s.com>
---
arch/mips/include/asm/barrier.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 1a99a6c5b5dd..f3b5aa0938c1 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -118,7 +118,17 @@ static inline void wmb(void)
#define nudge_writes() mb()
#endif
-#define __smp_mb__before_atomic() __smp_mb__before_llsc()
+/*
+ * In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have
+ * a completion barrier immediately preceding the LL instruction. Therefore we
+ * can skip emitting a barrier from __smp_mb__before_atomic().
+ */
+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
+# define __smp_mb__before_atomic()
+#else
+# define __smp_mb__before_atomic() __smp_mb__before_llsc()
+#endif
+
#define __smp_mb__after_atomic() smp_llsc_mb()
static inline void sync_ginv(void)
--
2.23.0
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