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Date:   Thu, 3 Oct 2019 12:25:32 +0530
From:   Jagan Teki <jagan@...rulasolutions.com>
To:     Icenowy Zheng <icenowy@...c.io>
Cc:     Maxime Ripard <mripard@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        Michael Trimarchi <michael@...rulasolutions.com>,
        linux-sunxi <linux-sunxi@...glegroups.com>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [linux-sunxi] Re: [PATCH v11 1/7] drm/sun4i: dsi: Fix TCON DRQ
 set bits

On Thu, Oct 3, 2019 at 12:21 PM Icenowy Zheng <icenowy@...c.io> wrote:
>
>
>
> 于 2019年10月3日 GMT+08:00 下午2:45:21, Jagan Teki <jagan@...rulasolutions.com> 写到:
> >The LCD timing definitions between Linux DRM vs Allwinner are
> >different,
> >below diagram shows this clear differences.
> >
> >           Active                 Front           Sync           Back
> >           Region                 Porch                          Porch
> ><-----------------------><----------------><--------------><-------------->
> >  //////////////////////|
> > ////////////////////// |
> >//////////////////////  |..................
> >................
> >                                           ________________
> ><----- [hv]display ----->
> ><------------- [hv]sync_start ------------>
> ><--------------------- [hv]sync_end ---------------------->
> ><-------------------------------- [hv]total
> >------------------------------>
> >
> ><----- lcd_[xy] -------->                <- lcd_[hv]spw ->
> >                                         <---------- lcd_[hv]bp --------->
> ><-------------------------------- lcd_[hv]t
> >------------------------------>
> >
> >The DSI driver misinterpreted the hbp term from the BSP code to refer
> >only to the backporch, when in fact it was backporch + sync. Thus the
> >driver incorrectly used the horizontal front porch plus sync in its
> >calculation of the DRQ set bit value, when it should not have included
> >the sync timing.
> >
> >Including additional sync timings leads to flip_done timed out as:
>
> I don't think attaching this error infomation is useful at all.

Since the error would be common irrespective of panels and it would
trigger from dsi controller, I thought this would be useful for
reference. I have had this conversation in previous version changes,
so I have added it. let me know if have any comments.

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