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Date: Mon, 7 Oct 2019 17:55:52 +0000 From: John Stultz <john.stultz@...aro.org> To: lkml <linux-kernel@...r.kernel.org> Cc: John Stultz <john.stultz@...aro.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Felipe Balbi <balbi@...nel.org>, Andy Shevchenko <andy.shevchenko@...il.com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Yu Chen <chenyu56@...wei.com>, Matthias Brugger <matthias.bgg@...il.com>, Chunfeng Yun <chunfeng.yun@...iatek.com>, linux-usb@...r.kernel.org, devicetree@...r.kernel.org Subject: [RFC][PATCH v2 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi Add necessary compatible flag for HiSi's DWC3 so dwc3-of-simple will probe. Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org> Cc: Felipe Balbi <balbi@...nel.org> Cc: Andy Shevchenko <andy.shevchenko@...il.com> Cc: Rob Herring <robh+dt@...nel.org> Cc: Mark Rutland <mark.rutland@....com> Cc: Yu Chen <chenyu56@...wei.com> Cc: Matthias Brugger <matthias.bgg@...il.com> Cc: Chunfeng Yun <chunfeng.yun@...iatek.com> Cc: linux-usb@...r.kernel.org Cc: devicetree@...r.kernel.org Signed-off-by: John Stultz <john.stultz@...aro.org> --- v2: Tweaked clock names as clk_usb3phy_ref didn't seem right. --- .../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt new file mode 100644 index 000000000000..3a3e5c320f2a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt @@ -0,0 +1,52 @@ +HiSi SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "clk_abb_usb" USB reference clk + "aclk_usb3otg" USB3 OTG aclk + +- assigned-clocks: Should be: + HI3660_ACLK_GATE_USB3OTG +- assigned-clock-rates: Should be: + 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG + +Optional properties: +- resets: Phandle to reset control that resets core and wrapper. + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Example device nodes: + + usb3: hisi_dwc3 { + compatible = "hisilicon,hi3660-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "clk_abb_usb", "aclk_usb3otg"; + + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229 000 000>; + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + dwc3: dwc3@...00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + dr_mode = "otg"; + + ... + }; + }; -- 2.17.1
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