linux-kernel - Re: [linux-sunxi] [PATCH] bus: sunxi-rsb: Make interrupt handling more robust

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Message-ID: <20191007152948.jgz6l4zmqjxqpzus@gilmour>
Date:   Mon, 7 Oct 2019 17:29:48 +0200
From:   Maxime Ripard <mripard@...nel.org>
To:     Chen-Yu Tsai <wens@...e.org>
Cc:     Samuel Holland <samuel@...lland.org>,
        Stephen Boyd <sboyd@...omium.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [linux-sunxi] [PATCH] bus: sunxi-rsb: Make interrupt handling
 more robust

Hi,

On Mon, Oct 07, 2019 at 11:19:06PM +0800, Chen-Yu Tsai wrote:
> On Sun, Aug 25, 2019 at 1:50 AM Samuel Holland <samuel@...lland.org> wrote:
> > The RSB controller has two registers for controlling interrupt inputs:
> > RSB_INTE, which has bits for each possible interrupt, and the global
> > interrupt enable bit in RSB_CTRL.
> >
> > Currently, we enable the bits in RSB_INTE before each transfer, but this
> > is unnecessary because we never disable them. Move the initialization of
> > RSB_INTE so it is done only once.
> >
> > We also set the global interrupt enable bit before each transfer. Unlike
> > other bits in RSB_CTRL, this bit is cleared by writing a zero. Thus, we
> > clear the bit in the post-timeout cleanup code, so note that in the
> > comment.
> >
> > However, if we do receive an interrupt, we do not clear the bit. Nor do
> > we clear interrupt statuses before starting a transfer. Thus, if some
> > other driver uses the RSB bus while Linux is suspended (as both Trusted
> > Firmware and SCP firmware do to control the PMIC), we receive spurious
> > interrupts upon resume. This causes false completion of a transfer, and
> > the next transfer starts prematurely, causing a LOAD_BSY condition. The
> > end result is that some transfers at resume fail with -EBUSY.
>
> If we are expecting the hardware to not be in the state we assume to be
> or left it in, then maybe we should also keep setting the interrupt enable
> bits on each transfer?
>
> Surely we expect to have exclusive use of the controller most of the time.
> If it's to handle suspend/resume, shouldn't we be adding power management
> callbacks instead? That would reset the controller to a known state when
> the system comes out of suspend, including clearing any pending interrupts.
>
> Maxime, anything you want to add? (BTW, Maxime switched email addresses.)

The patch looks pretty harmless, so we can merge it, but if we're
going to share the RSB between those components, we should probably
use the hardware spinlocks as well.

Maxime

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