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Message-ID: <20191008154408.GC20318@infradead.org>
Date: Tue, 8 Oct 2019 08:44:08 -0700
From: Christoph Hellwig <hch@...radead.org>
To: Atish Patra <atish.patra@....com>
Cc: linux-kernel@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
Richard Fontana <rfontana@...hat.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Palmer Dabbelt <palmer@...ive.com>,
Johan Hovold <johan@...nel.org>,
Alexandre Ghiti <aghiti@...em.com>,
Thomas Gleixner <tglx@...utronix.de>,
Paul Walmsley <paul.walmsley@...ive.com>,
Anup Patel <anup@...infault.org>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-riscv@...ts.infradead.org
Subject: Re: [v1 PATCH 2/2] RISC-V: Consolidate isa correctness check
> +int riscv_read_check_isa(struct device_node *node, const char **isa)
> +{
> + u32 hart;
> +
> + if (of_property_read_u32(node, "reg", &hart)) {
> + pr_warn("Found CPU without hart ID\n");
> + return -ENODEV;
> + }
> +
> + if (of_property_read_string(node, "riscv,isa", isa)) {
> + pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n",
> + hart);
> + return -ENODEV;
> + }
> +
> + /*
> + * Linux doesn't support rv32e or rv128i, and we only support booting
> + * kernels on harts with the same ISA that the kernel is compiled for.
> + */
> +#if defined(CONFIG_32BIT)
> + if (strncmp(*isa, "rv32i", 5) != 0)
> + return -ENODEV;
> +#elif defined(CONFIG_64BIT)
> + if (strncmp(*isa, "rv64i", 5) != 0)
> + return -ENODEV;
> +#endif
Using IS_ENABLED here would clean the checks up a bit.
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1ade9a49347..eaad5aa07403 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -38,10 +38,8 @@ void riscv_fill_hwcap(void)
> if (riscv_of_processor_hartid(node) < 0)
> continue;
>
> - if (of_property_read_string(node, "riscv,isa", &isa)) {
> - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> + if (riscv_read_check_isa(node, &isa) < 0)
> continue;
Do we really get rid of warnings if we didn't find anything proper?
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