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Message-Id: <20191014071327.28961-1-wen.he_1@nxp.com>
Date: Mon, 14 Oct 2019 15:13:27 +0800
From: Wen He <wen.he_1@....com>
To: linux-devel@...ux.nxdi.nxp.com, Shawn Guo <shawnguo@...nel.org>,
Li Yang <leoyang.li@....com>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Cc: Wen He <wen.he_1@....com>
Subject: [v3] arm64: dts: ls1028a: Update the property of the DT node dpclk
Update the property #clock-cells = <1> to #clock-cells = <0> of the
dpclk, since the Display output pixel clock driver provides single
clock output.
Signed-off-by: Wen He <wen.he_1@....com>
---
change in v3:
- according the maintainer correction node name
- update the commit message
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 51fa8f57fdac..616b150a15aa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -82,7 +82,7 @@
dpclk: clock-controller@...0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&osc_27m>;
};
@@ -665,7 +665,7 @@
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
- clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
+ clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
<&clockgen 2 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
--
2.17.1
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