linux-kernel - Re: [PATCH v3 3/3] mtd: spi-nor: cadence-quadspi: disable the auto-poll for Intel LGM

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Date:   Wed, 16 Oct 2019 16:53:17 +0800
From:   "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>
To:     Vignesh Raghavendra <vigneshr@...com>,
        linux-mtd@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        dwmw2@...radead.org, computersforpeace@...il.com, richard@....at,
        jwboyer@...il.com, boris.brezillon@...e-electrons.com,
        cyrille.pitchen@...el.com, david.oberhollenzer@...ma-star.at,
        miquel.raynal@...tlin.com, tudor.ambarus@...il.com,
        andriy.shevchenko@...el.com, cheol.yong.kim@...el.com,
        qi-ming.wu@...el.com
Subject: Re: [PATCH v3 3/3] mtd: spi-nor: cadence-quadspi: disable the
 auto-poll for Intel LGM

Hi Vignesh,

      Thank you for the review comments.

On 16/10/2019 4:40 PM, Vignesh Raghavendra wrote:
>
> On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
>>
>> On Intel's Lightning Mountain(LGM) SoC QSPI controller do not auto-poll.
>> This patch introduces to properly disable the auto-polling feature to
> This patch disables auto polling when direct access mode is disabled
> which should be noted in the commit message.
will add it.
>> improve the performance of cadence-quadspi.
> How does this improve performance of cadence-quadspi? I would expect HW
> auto-polling to be faster than SW polling.
During the bring-up time observed this, once again verify it on my setup.
Agreed, you are correct HW auto-polling is faster than SW polling.
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
>> ---
>>   drivers/mtd/spi-nor/cadence-quadspi.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 73b9fbd1508a..60998eaad1cc 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -135,6 +135,8 @@ struct cqspi_driver_platdata {
>>   #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
>>   #define CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
>>   
>> +#define CQSPI_REG_WR_COMPLETION_CTRL		0x38
>> +#define CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL	BIT(14)
>>   #define CQSPI_REG_WR_INSTR			0x08
>>   #define CQSPI_REG_WR_INSTR_OPCODE_LSB		0
>>   #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
>> @@ -471,6 +473,18 @@ static int cqspi_command_write_addr(struct spi_nor *nor,
>>   	return cqspi_exec_flash_cmd(cqspi, reg);
>>   }
>>   
>> +static int cqspi_disable_auto_poll(struct cqspi_st *cqspi)
>> +{
>> +	void __iomem *reg_base = cqspi->iobase;
>> +	unsigned int reg;
>> +
>> +	reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
>> +	reg |= CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL;
>> +	writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
>> +
>> +	return 0;
>> +}
>> +
>>   static int cqspi_read_setup(struct spi_nor *nor)
>>   {
>>   	struct cqspi_flash_pdata *f_pdata = nor->priv;
>> @@ -508,6 +522,11 @@ static int cqspi_read_setup(struct spi_nor *nor)
>>   	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
>>   	reg |= (nor->addr_width - 1);
>>   	writel(reg, reg_base + CQSPI_REG_SIZE);
>> +
>> +	/* Disable auto-polling */
>> +	if (!f_pdata->use_direct_mode)
>> +		cqspi_disable_auto_poll(cqspi);
>> +
>>   	return 0;
>>   }
>>   
> Hmmm.. There is no need to disable polling for every read/write
> operation. It should be enough to do it once in cqspi_controller_init()
sure, move to cqspi_controller_init() .
---
Regards
Vadivel
>
>
>> @@ -627,6 +646,11 @@ static int cqspi_write_setup(struct spi_nor *nor)
>>   	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
>>   	reg |= (nor->addr_width - 1);
>>   	writel(reg, reg_base + CQSPI_REG_SIZE);
>> +
>> +	/* Disable auto-polling */
>> +	if (!f_pdata->use_direct_mode)
>> +		cqspi_disable_auto_poll(cqspi);
>> +
>>   	return 0;
>>   }
>>   
>>