[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAGb2v67QrTJjSO99UNs-=3ZZnK948am11=izRTHT6gZ06E28eA@mail.gmail.com>
Date: Wed, 16 Oct 2019 22:54:27 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Maxime Ripard <mripard@...nel.org>
Cc: Alistair Francis <alistair@...stair23.me>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
alistair23@...il.com
Subject: Re: [PATCH] arm64: dts: sun50i: sopine-baseboard: Expose serial1,
serial2 and serial3
On Wed, Oct 16, 2019 at 10:49 PM Maxime Ripard <mripard@...nel.org> wrote:
>
> Hi,
>
> On Sat, Oct 12, 2019 at 01:05:24PM -0700, Alistair Francis wrote:
> > Follow what the sun50i-a64-pine64.dts does and expose all 5 serial
> > connections.
> >
> > Signed-off-by: Alistair Francis <alistair@...stair23.me>
> > ---
> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 25 +++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
> > index 124b0b030b28..49c37b21ab36 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
> > @@ -56,6 +56,10 @@
> > aliases {
> > ethernet0 = &emac;
> > serial0 = &uart0;
> > + serial1 = &uart1;
> > + serial2 = &uart2;
> > + serial3 = &uart3;
> > + serial4 = &uart4;
> > };
> >
> > chosen {
> > @@ -280,6 +284,27 @@
> > };
> > };
> >
> > +/* On Pi-2 connector */
> > +&uart2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart2_pins>;
> > + status = "disabled";
> > +};
> > +
> > +/* On Euler connector */
> > +&uart3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart3_pins>;
> > + status = "disabled";
> > +};
> > +
> > +/* On Euler connector, RTS/CTS optional */
> > +&uart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart4_pins>;
> > + status = "disabled";
> > +};
>
> Since these are all the default muxing, maybe we should just set that
> in the DTSI?
Maybe not, since people may want to only use RX/TX, and leave the other
two pins for GPIO?
ChenYu
Powered by blists - more mailing lists