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Message-ID: <5da9ccba.1c69fb81.3cae7.0064@mx.google.com>
Date: Fri, 18 Oct 2019 07:31:21 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Mark Rutland <mark.rutland@....com>,
Rob Herring <robh+dt@...nel.org>,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
devicetree@...r.kernel.org
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
Rajendra Nayak <rnayak@...eaurora.org>,
Rishabh Bhatnagar <rishabhb@...eaurora.org>,
Doug Anderson <dianders@...omium.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Subject: Re: [PATCH 1/2] soc: qcom: llcc: Add configuration data for SC7180
Quoting Sai Prakash Ranjan (2019-10-18 06:57:08)
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 4bd982a294ce..4acb52f8536b 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -91,6 +91,13 @@ struct qcom_llcc_config {
> int size;
> };
>
> +static struct llcc_slice_config sc7180_data[] = {
const?
> + { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
> + { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
> + { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
> + { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
> +};
> +
> static struct llcc_slice_config sdm845_data[] = {
This one should be const too I guess but it's not part of this patch.
> { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
> { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
> @@ -112,6 +119,11 @@ static struct llcc_slice_config sdm845_data[] = {
> { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
> };
>
> +static const struct qcom_llcc_config sc7180_cfg = {
> + .sct_data = sc7180_data,
> + .size = ARRAY_SIZE(sc7180_data),
> +};
> +
> static const struct qcom_llcc_config sdm845_cfg = {
> .sct_data = sdm845_data,
> .size = ARRAY_SIZE(sdm845_data),
Otherwise looks OK to me.
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