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Message-ID: <5da9cd3a.1c69fb81.95e9.e5e2@mx.google.com>
Date:   Fri, 18 Oct 2019 07:33:29 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        Mark Rutland <mark.rutland@....com>, rnayak@...eaurora.org,
        suzuki.poulose@....com, catalin.marinas@....com,
        linux-arm-kernel <linux-arm-kernel-bounces@...ts.infradead.org>,
        linux-kernel@...r.kernel.org, jeremy.linton@....com,
        bjorn.andersson@...aro.org, linux-arm-msm@...r.kernel.org,
        andrew.murray@....com, will@...nel.org, dave.martin@....com,
        linux-arm-kernel@...ts.infradead.org, marc.w.gonzalez@...e.fr
Subject: Re: Relax CPU features sanity checking on heterogeneous architectures

Quoting Marc Zyngier (2019-10-18 00:20:56)
> 
> If this SoC is anythinig like SM8150, 32bit guests will be hit and 
> miss,
> depending on the CPU your guest runs on, or is migrated to. We need to
> either drop capabilities from the 32bit-capable CPU, or prevent the
> non-32bit capable CPU from booting if a 32bit guest has been started.
> 
> You just have to hope that the kernel is entered at EL2, and that QC's
> "value add" has been moved somewhere else...
> 

Ok that's good.

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