[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <cf1f6d9c-4145-ef12-4b88-737fe7a5de8c@linux.intel.com>
Date: Mon, 21 Oct 2019 16:31:09 +0800
From: Dilip Kota <eswara.kota@...ux.intel.com>
To: Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>,
"jingoohan1@...il.com" <jingoohan1@...il.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"andrew.murray@....com" <andrew.murray@....com>,
"robh@...nel.org" <robh@...nel.org>,
"martin.blumenstingl@...glemail.com"
<martin.blumenstingl@...glemail.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"hch@...radead.org" <hch@...radead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"andriy.shevchenko@...el.com" <andriy.shevchenko@...el.com>,
"cheol.yong.kim@...el.com" <cheol.yong.kim@...el.com>,
"chuanhua.lei@...ux.intel.com" <chuanhua.lei@...ux.intel.com>,
"qi-ming.wu@...el.com" <qi-ming.wu@...el.com>
Subject: Re: [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective
dt-binding yaml file
Hi Gustavo Pimentel,
On 10/21/2019 4:08 PM, Gustavo Pimentel wrote:
> Hi,
>
>
> On Mon, Oct 21, 2019 at 7:39:17, Dilip Kota <eswara.kota@...ux.intel.com>
> wrote:
>
>> Intel PCIe is synopsys based controller utilizes the Designware
> Please do this general replacement in all your patches.
>
> s/synopsys/Synopsys
>
> and
>
> s/Designware/DesignWare
Sure, i will update it in the next patch version.
(In the all other patches naming is proper, i got missed it here.)
I will ensure and take care of it.
Regards,
Dilip
>
>> framework for host initialization and intel application
>> specific register configurations.
>>
>> Changes on v4:
>> Add lane resizing API in PCIe DesignWare driver.
>> Intel PCIe driver uses it for lane resizing which
>> is being exposed through sysfs attributes.
>> Add Intel PCIe sysfs attributes is in separate patch.
>> Address review comments given on v3.
>>
>> Changes on v3:
>> Compared to v2, map_irq() patch is removed as it is no longer
>> required for Intel PCIe driver. Intel PCIe driver does platform
>> specific interrupt configuration during core initialization. So
>> changed the subject line too.
>> Address v2 review comments for DT binding and PCIe driver
>>
>> Dilip Kota (3):
>> dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
>> dwc: PCI: intel: PCIe RC controller driver
>> pci: intel: Add sysfs attributes to configure pcie link
>>
>> .../devicetree/bindings/pci/intel-gw-pcie.yaml | 135 ++++
>> drivers/pci/controller/dwc/Kconfig | 10 +
>> drivers/pci/controller/dwc/Makefile | 1 +
>> drivers/pci/controller/dwc/pcie-designware.c | 43 ++
>> drivers/pci/controller/dwc/pcie-designware.h | 15 +
>> drivers/pci/controller/dwc/pcie-intel-gw.c | 700 +++++++++++++++
>> include/uapi/linux/pci_regs.h | 1 +
>> 7 files changed, 905 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>> create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
>>
>> --
>> 2.11.0
>
Powered by blists - more mailing lists