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Message-ID: <20191021150345.igdye4kv35nsk4ox@outlook.office365.com>
Date:   Mon, 21 Oct 2019 15:03:53 +0000
From:   "Siqueira, Rodrigo" <Rodrigo.Siqueira@....com>
To:     "Wentland, Harry" <Harry.Wentland@....com>,
        "Li, Sun peng (Leo)" <Sunpeng.Li@....com>,
        "Deucher, Alexander" <Alexander.Deucher@....com>,
        "Cornij, Nikola" <Nikola.Cornij@....com>,
        Jani Nikula <jani.nikula@...ux.intel.com>,
        Manasi Navare <manasi.d.navare@...el.com>,
        Ville Syrjälä <ville.syrjala@...ux.intel.com>,
        Rodrigo Siqueira <rodrigosiqueiramelo@...il.com>
CC:     "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "amd-gfx@...ts.freedesktop.org" <amd-gfx@...ts.freedesktop.org>
Subject: [PATCH] drm: Fix DSC throughput mode 0 mask definition

Commit d7cd0e05 introduced a change at DP_DSC_THROUGHPUT_MODE_0_170
which is not aligned with the spec. This commit replace 15 << 4 by
15 << 0 for DP_DSC_THROUGHPUT_MODE_0_170 in order to make it follow the
specification.

Cc: Harry Wentland <harry.wentland@....com>
Cc: Leo Li <sunpeng.li@....com>
Cc: Alex Deucher <alexander.deucher@....com>
Cc: Nikola Cornij <nikola.cornij@....com>
Cc: Jani Nikula <jani.nikula@...ux.intel.com>
Cc: Manasi Navare <manasi.d.navare@...el.com>
Cc: Ville Syrjälä <ville.syrjala@...ux.intel.com>
Fixes: d7cd0e053b1 (drm/amd/display: Add 170Mpix/sec DSC throughput support)
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@....com>
---
 include/drm/drm_dp_helper.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cfadeeef8492..52024049c59e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -306,7 +306,7 @@
 # define DP_DSC_THROUGHPUT_MODE_0_900       (12 << 0)
 # define DP_DSC_THROUGHPUT_MODE_0_950       (13 << 0)
 # define DP_DSC_THROUGHPUT_MODE_0_1000      (14 << 0)
-# define DP_DSC_THROUGHPUT_MODE_0_170       (15 << 4)
+# define DP_DSC_THROUGHPUT_MODE_0_170       (15 << 0) /* 1.4a */
 # define DP_DSC_THROUGHPUT_MODE_1_MASK      (0xf << 4)
 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT     4
 # define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0
-- 
2.23.0

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