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Message-Id: <CEA29A3B-4116-4FE3-8E18-0C97353688DC@goldelico.com>
Date: Mon, 21 Oct 2019 17:45:06 +0200
From: "H. Nikolaus Schaller" <hns@...delico.com>
To: Rob Herring <robh+dt@...nel.org>
Cc: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Mark Rutland <mark.rutland@....com>,
Benoît Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
dri-devel <dri-devel@...ts.freedesktop.org>,
devicetree@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-omap <linux-omap@...r.kernel.org>,
Discussions about the Letux Kernel
<letux-kernel@...nphoenux.org>, kernel@...a-handheld.com
Subject: Re: [PATCH 1/7] dt-bindings: gpu: pvrsgx: add initial bindings
Hi Rob,
> Am 21.10.2019 um 17:07 schrieb Rob Herring <robh+dt@...nel.org>:
>
> On Fri, Oct 18, 2019 at 1:46 PM H. Nikolaus Schaller <hns@...delico.com> wrote:
>>
>> The Imagination PVR/SGX GPU is part of several SoC from
>> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo
>> and others.
>>
>> Here we describe how the SGX processor is interfaced to
>> the SoC (registers, interrupt etc.).
>>
>> Clock, Reset and power management should be handled
>> by the parent node.
>
> That's TI specific.
Ok. Would this be better:
Clock, Reset and power management is not handled by this binding
and can e.g. be described by the parent node.
>
>>
>> Signed-off-by: H. Nikolaus Schaller <hns@...delico.com>
>> ---
>> .../devicetree/bindings/gpu/img,pvrsgx.txt | 76 +++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.txt
>
> Please make this DT schema format.
Is there a tutorial or a tool to convert?
I have only seen that a new format exists but zero experience.
>
>> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt b/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt
>> new file mode 100644
>> index 000000000000..4ad87c075791
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt
>> @@ -0,0 +1,76 @@
>> +Imagination PVR/SGX GPU
>> +
>> +Only the Imagination SGX530, SGX540 and SGX544 GPUs are currently covered by this binding.
>> +
>> +Required properties:
>> +- compatible: Should be one of
>> + "img,sgx530-121", "img,sgx530", "ti,omap-omap3-sgx530-121";
>> + - BeagleBoard ABC, OpenPandora 600MHz
>> + "img,sgx530-125", "img,sgx530", "ti,omap-omap3-sgx530-125";
>> + - BeagleBoard XM, GTA04, OpenPandora 1GHz
>> + "img,sgx530-125", "img,sgx530", "ti,omap-am3517-sgx530-125";
>> + "img,sgx530-125", "img,sgx530", "ti,omap-am335x-sgx530-125";
>> + - BeagleBone Black
>> + "img,sgx540-120", "img,sgx540", "ti,omap-omap4-sgx540-120";
>> + - Pandaboard (ES)
>> + "img,sgx544-112", "img,sgx544", "ti,omap-omap4-sgx544-112";
>> + "img,sgx544-116", "img,sgx544", "ti,omap-omap5-sgx544-116";
>> + - OMAP5 UEVM, Pyra Handheld
>> + "img,sgx544-116", "img,sgx544", "ti,omap-dra7-sgx544-116";
>
> The order here is wrong. Should be most specific first.
>
> Drop 'omap-' from the compatible.
Ok, yes. Seems to be redundant since omap is from ti only...
>
>> +
>> + For further study:
>> + "ti,omap-am3517-sgx530-?"
>> + "ti,omap-am43xx-sgx530-?"
>> + "ti,ti43xx-sgx"
>> + "ti,ti81xx-sgx"
>> + "img,jz4780-sgx5??-?"
>> + "intel,poulsbo-sgx?"
>> + "intel,cedarview-sgx?"
>> + "sunxi,sgx-544-?" - Banana-Pi-M3 (Allwinner A83T)
>
> Just drop these.
Well, the driver code package we have seems to support them and the idea (dream?)
is to make it a generic driver compatible to all of them.
So we could leave it out and add later (in the hope that it does not get
forgotten).
>
>> +
>> + The "ti,omap..." entries are needed temporarily to handle SoC
>> + specific builds of the kernel module.
>> +
>> + In the long run, only the "img,sgx..." entry should suffice
>> + to match a generic driver for all architectures and driver
>> + code can dynamically find out on which SoC it is running.
>
> Drop this. Which compatible an OS matches on is not relevant to the
> binding. And 'temporarily' is wrong as the SoC specific compatible
> strings are what are used for handling errata or other integration
> specific things.
The idea behind this is that a driver can finally find out by different
means which SoC it is connected to.
At the moment we have to build different pvrsrvkm.ko for each one since
there is no "generic" driver yet.
So in the long run only img,sgx... should be there. And even this might
be boiled down to img,sgx5 (assuming that even 530/540/544) is detectable.
But at the moment we are not able to create working code without the
mix of soc and sgx versioning.
Basically it boils down if we want a basis that works today and is prepared
for tomorrow, or if we have to decide for either today or future and can't
bridge between.
>
>> +
>> +
>> +- reg: Physical base addresses and lengths of the register areas.
>
> How many?
I assume there is only one. At least it suffices to make the existing
driver work with it.
>
>> +- reg-names: Names for the register areas.
>
> If only 1 as the example suggests, then you don't need this.
ok.
>
>> +- interrupts: The interrupt numbers.
>> +
>> +Optional properties:
>> +- timer: the timer to be used by the driver.
>
> Needs a better description and vendor prefix at least.
I am not yet sure if it is vendor specific or if all
SGX implementations need some timer.
>
> Why is this needed rather than using the OS's timers?
Because nobody understands the current (out of tree and
planned for staging) driver well enough what the timer
is doing. It is currently hard coded that some omap refer
to timer7 and others use timer11.
>
>> +- img,cores: number of cores. Defaults to <1>.
>
> Not discoverable?
Not sure if it is. This is probably available in undocumented
registers of the sgx.
>
>> +
>> +/ {
>> + ocp {
>> + sgx_module: target-module@...00000 {
>
> This is TI specific and this binding covers other chips in theory at
> least. This part is outside the scope
Ok, it is the only example where we know that it works. So we do not
yet know how the GPU integration would have to look like for e.g. CI20
or BananaPi M3 (which are not that well converted to device tree like OMAP).
This project is quite at the beginning...
>
>> + compatible = "ti,sysc-omap4", "ti,sysc";
>> + reg = <0x5600fe00 0x4>,
>> + <0x5600fe10 0x4>;
>
> How does it work that these registers overlap the GPU registers?
Both drivers have access to these registers. Likely, the gpu driver
ignores them and does access other ranges.
>
>> + reg-names = "rev", "sysc";
>> + ti,sysc-midle = <SYSC_IDLE_FORCE>,
>> + <SYSC_IDLE_NO>,
>> + <SYSC_IDLE_SMART>;
>> + ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>> + <SYSC_IDLE_NO>,
>> + <SYSC_IDLE_SMART>;
>> + clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
>> + clock-names = "fck";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x56000000 0x2000000>;
>> +
>> + sgx@...0 {
>
> gpu@...
Yes, is better to name it according to the function.
>
>
>
>> + compatible = "img,sgx544-116", "img,sgx544", "ti,omap-omap5-sgx544-116";
>> + reg = <0xfe00 0x200>;
>> + reg-names = "sgx";
>> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + timer = <&timer11>;
>> + img,cores = <2>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.19.1
BR and thanks,
Nikolaus
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