lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <6bc9645d-28df-bcef-e94d-498516fc4ac2@ti.com>
Date:   Tue, 22 Oct 2019 16:05:32 +0300
From:   Roger Quadros <rogerq@...com>
To:     Kishon Vijay Abraham I <kishon@...com>, Jyri Sarha <jsarha@...com>
CC:     Anil Varughese <aniljoy@...ence.com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH 00/13] PHY: Add support for SERDES in TI's J721E SoC

Hi,

On 16/10/2019 14:31, Kishon Vijay Abraham I wrote:
> TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII.
> TI has a wrapper named WIZ to control input signals to Sierra and
> Torrent SERDES.
> 
> This patch series:
>   1) Add support to WIZ module present in TI's J721E SoC
>   2) Adapt Cadence Sierra PHY driver to be used for J721E SoC
> 
> Anil Varughese (1):
>    phy: cadence: Sierra: Configure both lane cdb and common cdb registers
>      for external SSC
> 
> Kishon Vijay Abraham I (12):
>    dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
>    phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional
>      resources
>    phy: cadence: Sierra: Use "regmap" for read and write to Sierra
>      registers
>    phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
>    phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
>    phy: cadence: Sierra: Modify register macro names to be in sync with
>      Sierra user guide
>    phy: cadence: Sierra: Get reset control "array" for each link
>    phy: cadence: Sierra: Check for PLL lock during PHY power on
>    phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
>    phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz
>    dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
>    phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

Tested USB3.0 on J7ES using this series.

Tested-by: Roger Quadros <rogerq@...com>

> 
>   .../bindings/phy/phy-cadence-sierra.txt       |  13 +-
>   .../bindings/phy/ti,phy-j721e-wiz.txt         |  95 ++
>   drivers/phy/cadence/phy-cadence-sierra.c      | 695 +++++++++++---
>   drivers/phy/ti/Kconfig                        |  15 +
>   drivers/phy/ti/Makefile                       |   1 +
>   drivers/phy/ti/phy-j721e-wiz.c                | 904 ++++++++++++++++++
>   6 files changed, 1585 insertions(+), 138 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
>   create mode 100644 drivers/phy/ti/phy-j721e-wiz.c
> 

-- 
cheers,
-roger
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ