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Date:   Tue, 22 Oct 2019 16:09:02 +0200
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Like Xu <like.xu@...ux.intel.com>, kvm@...r.kernel.org
Cc:     peterz@...radead.org, like.xu@...el.com,
        linux-kernel@...r.kernel.org, jmattson@...gle.com,
        sean.j.christopherson@...el.com, wei.w.wang@...el.com,
        kan.liang@...el.com
Subject: Re: [PATCH v3 6/6] KVM: x86/vPMU: Add lazy mechanism to release
 perf_event per vPMC

On 22/10/19 14:00, Like Xu wrote:
> 
> Second, the structure of pmu->pmc_in_use is in the following format:
> 
>   Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
>             [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
>   AMD:   [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters

Sorry---I confused INTEL_PMC_MAX_FIXED and INTEL_PMC_IDX_FIXED.

The patches look good, I'll give them another look since I obviously
wasn't very much awake when reviewing them.

Paolo

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