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Message-Id: <1571763622-29281-3-git-send-email-radhey.shyam.pandey@xilinx.com>
Date: Tue, 22 Oct 2019 22:30:18 +0530
From: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
To: vkoul@...nel.org, robh+dt@...nel.org, mark.rutland@....com,
dan.j.williams@...el.com, michal.simek@...inx.com,
anirudha.sarangi@...inx.com, nick.graumann@...il.com,
andrea.merello@...il.com, appana.durga.rao@...inx.com,
mcgrof@...nel.org
Cc: dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
Subject: [PATCH -next 2/6] dt-bindings: dmaengine: xilinx_dma: Fix formatting and style
Trivial formatting(keep compatible string one per line, caps change etc).
It doesn't modify the content of the binding.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
---
Changes since RFC:
New patch. Trivial formatting (compatible string one per line) as
suggested by Rob in MCDMA RFC series.
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index 99d06f9..d4ba1cb 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -12,8 +12,10 @@ Xilinx AXI CDMA engine, it does transfers between memory-mapped source
address and a memory-mapped destination address.
Required properties:
-- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
- "xlnx,axi-cdma-1.00.a""
+- compatible: Should be one of-
+ "xlnx,axi-vdma-1.00.a"
+ "xlnx,axi-dma-1.00.a"
+ "xlnx,axi-cdma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length.
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
@@ -29,7 +31,7 @@ Required properties:
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
For CDMA:
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
- FOR AXIDMA:
+ For AXIDMA:
Required elements: "s_axi_lite_aclk"
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
"m_axi_sg_aclk"
--
2.7.4
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