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Message-Id: <20191022192038.30094-1-rpimentel.silva@gmail.com>
Date: Tue, 22 Oct 2019 16:20:34 -0300
From: Rogerio Pimentel da Silva <rpimentel.silva@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Carlo Caione <ccaione@...libre.com>,
Abel Vesa <abel.vesa@....com>,
Anson Huang <Anson.Huang@....com>,
Daniel Baluta <daniel.baluta@....com>,
Baruch Siach <baruch@...s.co.il>,
Andrey Smirnov <andrew.smirnov@...il.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: rpimentel.silva@...il.com
Subject: [PATCH] arm64: dts: imx8mq-evk: Add remote control
Add remote control to i.MX8M EVK device tree.
The rc protocol must be selected by writing to:
/sys/devices/platform/ir-receiver/rc/rc0/protocols
On my tests, I used "nec" rc protocol:
echo nec > protocols
Tested using evetest:
evtest /dev/input/event0
Output log for each key pressed:
Event:
time 1568122608.267845, -------------- SYN_REPORT ------------
Event:
time 1568122610.503835, type 4 (EV_MSC), code 4 (MSC_SCAN), value 440
Signed-off-by: Rogerio Pimentel da Silva <rpimentel.silva@...il.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 6ede46f7d45b..bd81e4a45ff5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -50,6 +50,13 @@
900000 0x1>;
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ir>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@@ -340,6 +347,12 @@
>;
};
+ pinctrl_ir: irgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
+ >;
+ };
+
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
--
2.17.1
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