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Message-Id: <1571937670-30828-2-git-send-email-zhouyanjie@zoho.com>
Date: Fri, 25 Oct 2019 01:21:09 +0800
From: Zhou Yanjie <zhouyanjie@...o.com>
To: linux-mips@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, dmaengine@...r.kernel.org,
devicetree@...r.kernel.org, robh+dt@...nel.org,
paul.burton@...s.com, vkoul@...nel.org, paul@...pouillou.net,
mark.rutland@....com, Zubair.Kakakhel@...tec.com,
dan.j.williams@...el.com
Subject: [PATCH 1/2 v2] dt-bindings: dmaengine: Add X1000 bindings.
Add the dmaengine bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@...o.com>
---
.../devicetree/bindings/dma/jz4780-dma.txt | 3 +-
include/dt-bindings/dma/x1000-dma.h | 40 ++++++++++++++++++++++
2 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/dma/x1000-dma.h
diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
index 636fcb2..ec89782 100644
--- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt
+++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
@@ -7,10 +7,11 @@ Required properties:
* ingenic,jz4725b-dma
* ingenic,jz4770-dma
* ingenic,jz4780-dma
+ * ingenic,x1000-dma
- reg: Should contain the DMA channel registers location and length, followed
by the DMA controller registers location and length.
- interrupts: Should contain the interrupt specifier of the DMA controller.
-- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
+- clocks: Should contain a clock specifier for the JZ4780/X1000 PDMA clock.
- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
DMA clients (see below).
diff --git a/include/dt-bindings/dma/x1000-dma.h b/include/dt-bindings/dma/x1000-dma.h
new file mode 100644
index 00000000..401e165
--- /dev/null
+++ b/include/dt-bindings/dma/x1000-dma.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * This header provides macros for X1000 DMA bindings.
+ *
+ * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@...o.com>
+ */
+
+#ifndef __DT_BINDINGS_DMA_X1000_DMA_H__
+#define __DT_BINDINGS_DMA_X1000_DMA_H__
+
+/*
+ * Request type numbers for the X1000 DMA controller (written to the DRTn
+ * register for the channel).
+ */
+#define X1000_DMA_DMIC_RX 0x5
+#define X1000_DMA_I2S0_TX 0x6
+#define X1000_DMA_I2S0_RX 0x7
+#define X1000_DMA_AUTO 0x8
+#define X1000_DMA_UART2_TX 0x10
+#define X1000_DMA_UART2_RX 0x11
+#define X1000_DMA_UART1_TX 0x12
+#define X1000_DMA_UART1_RX 0x13
+#define X1000_DMA_UART0_TX 0x14
+#define X1000_DMA_UART0_RX 0x15
+#define X1000_DMA_SSI0_TX 0x16
+#define X1000_DMA_SSI0_RX 0x17
+#define X1000_DMA_MSC0_TX 0x1a
+#define X1000_DMA_MSC0_RX 0x1b
+#define X1000_DMA_MSC1_TX 0x1c
+#define X1000_DMA_MSC1_RX 0x1d
+#define X1000_DMA_PCM0_TX 0x20
+#define X1000_DMA_PCM0_RX 0x21
+#define X1000_DMA_SMB0_TX 0x24
+#define X1000_DMA_SMB0_RX 0x25
+#define X1000_DMA_SMB1_TX 0x26
+#define X1000_DMA_SMB1_RX 0x27
+#define X1000_DMA_SMB2_TX 0x28
+#define X1000_DMA_SMB2_RX 0x29
+
+#endif /* __DT_BINDINGS_DMA_X1000_DMA_H__ */
--
2.7.4
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