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Message-ID: <20191025200603.GA10839@bogus>
Date: Fri, 25 Oct 2019 15:06:04 -0500
From: Rob Herring <robh@...nel.org>
To: Roger Quadros <rogerq@...com>
Cc: kishon@...com, aniljoy@...ence.com, adouglas@...ence.com,
nsekhar@...com, jsarha@...com, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C
dir GPIO
On Thu, Oct 24, 2019 at 02:40:41PM +0300, Roger Quadros wrote:
> This is an optional GPIO, if specified will be used to
> swap lane 0 and lane 1 based on GPIO status. This is required
> to achieve plug flip support for USB Type-C.
>
> Type-C companions typically need some time after the cable is
> plugged before and before they reflect the correct status of
> Type-C plug orientation on the DIR line.
>
> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
> of 100 ms (min) to 200 ms (max).
>
> Allow the DT node to specify the time (in ms) that we need
> to wait before sampling the DIR line.
>
> Signed-off-by: Roger Quadros <rogerq@...com>
> Cc: Rob Herring <robh@...nel.org>
> ---
> .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> index 8a1eccee6c1d..5dab0010bcdf 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> @@ -53,6 +53,21 @@ properties:
> assigned-clock-parents:
> maxItems: 2
>
> + typec-dir-gpios:
TI specific or could be generic?
> + maxItems: 1
> + description:
> + GPIO to signal Type-C cable orientation for lane swap.
> + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
> + achieve the funtionality of an exernal type-C plug flip mux.
s/exernal/external/
> +
> + typec-dir-debounce:
Needs '-ms' suffix.
> + $ref: '/schemas/types.yaml#/definitions/uint32'
then you can drop this because standard units have type already.
> + description:
> + Number of milliseconds to wait before sampling
> + typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
> + Type-C spec states minimum CC pin debounce of 100 ms and maximum
> + of 200 ms.
Express this as constraints:
minimum: 100
maximum: 200
default: ???
If the spec minimum is 100ms, then doesn't sampling ASAP violate the
spec?
> +
> patternProperties:
> "^pll[0|1]_refclk$":
> type: object
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
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