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Message-ID: <AADFC41AFE54684AB9EE6CBC0274A5D19D5CDC60@SHSMSX104.ccr.corp.intel.com>
Date: Fri, 25 Oct 2019 06:40:09 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Jacob Pan <jacob.jun.pan@...ux.intel.com>,
Lu Baolu <baolu.lu@...ux.intel.com>
CC: "iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
LKML <linux-kernel@...r.kernel.org>,
Joerg Roedel <joro@...tes.org>,
"David Woodhouse" <dwmw2@...radead.org>,
Alex Williamson <alex.williamson@...hat.com>,
Jean-Philippe Brucker <jean-philippe@...aro.com>,
"Liu, Yi L" <yi.l.liu@...el.com>,
"Raj, Ashok" <ashok.raj@...el.com>,
Christoph Hellwig <hch@...radead.org>,
"Jonathan Cameron" <jic23@...nel.org>,
Eric Auger <eric.auger@...hat.com>
Subject: RE: [PATCH v7 03/11] iommu/vt-d: Add custom allocator for IOASID
> From: Jacob Pan [mailto:jacob.jun.pan@...ux.intel.com]
> Sent: Friday, October 25, 2019 12:43 PM
>
> Hi Baolu,
>
> Thanks for the review. please see my comments inline.
>
> On Fri, 25 Oct 2019 10:30:48 +0800
> Lu Baolu <baolu.lu@...ux.intel.com> wrote:
>
> > Hi Jacob,
> >
> > On 10/25/19 3:54 AM, Jacob Pan wrote:
> > > When VT-d driver runs in the guest, PASID allocation must be
> > > performed via virtual command interface. This patch registers a
> > > custom IOASID allocator which takes precedence over the default
> > > XArray based allocator. The resulting IOASID allocation will always
> > > come from the host. This ensures that PASID namespace is system-
> > > wide.
> > >
> > > Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>
> > > Signed-off-by: Liu, Yi L <yi.l.liu@...el.com>
> > > Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> > > ---
> > > drivers/iommu/Kconfig | 1 +
> > > drivers/iommu/intel-iommu.c | 67
> > > +++++++++++++++++++++++++++++++++++++++++++++
> > > include/linux/intel-iommu.h | 2 ++ 3 files changed, 70
> > > insertions(+)
> > >
> > > diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
> > > index fd50ddffffbf..961fe5795a90 100644
> > > --- a/drivers/iommu/Kconfig
> > > +++ b/drivers/iommu/Kconfig
> > > @@ -211,6 +211,7 @@ config INTEL_IOMMU_SVM
> > > bool "Support for Shared Virtual Memory with Intel IOMMU"
> > > depends on INTEL_IOMMU && X86
> > > select PCI_PASID
> > > + select IOASID
> > > select MMU_NOTIFIER
> > > help
> > > Shared Virtual Memory (SVM) provides a facility for
> > > devices diff --git a/drivers/iommu/intel-iommu.c
> > > b/drivers/iommu/intel-iommu.c index 3f974919d3bd..ced1d89ef977
> > > 100644 --- a/drivers/iommu/intel-iommu.c
> > > +++ b/drivers/iommu/intel-iommu.c
> > > @@ -1706,6 +1706,9 @@ static void free_dmar_iommu(struct
> > > intel_iommu *iommu) if (ecap_prs(iommu->ecap))
> > > intel_svm_finish_prq(iommu);
> > > }
> > > + if (ecap_vcs(iommu->ecap) && vccap_pasid(iommu->vccap))
> > > +
> > > ioasid_unregister_allocator(&iommu->pasid_allocator);
> >
> > Since scalable mode is disabled if pasid allocator failed to register,
> > add sm_support(iommu) check here will be better.
> >
> I was thinking to be symmetric with register call, checking for the
> same conditions. Also, I like your advice below to only disable SVA
> instead of scalable mode.
> > > +
> > > #endif
> > > }
> > >
> > > @@ -4910,6 +4913,44 @@ static int __init
> > > probe_acpi_namespace_devices(void) return 0;
> > > }
> > >
> > > +#ifdef CONFIG_INTEL_IOMMU_SVM
> > > +static ioasid_t intel_ioasid_alloc(ioasid_t min, ioasid_t max,
> > > void *data) +{
> > > + struct intel_iommu *iommu = data;
> > > + ioasid_t ioasid;
> > > +
> > > + /*
> > > + * VT-d virtual command interface always uses the full 20
> > > bit
> > > + * PASID range. Host can partition guest PASID range based
> > > on
> > > + * policies but it is out of guest's control.
> > > + */
> > > + if (min < PASID_MIN || max > intel_pasid_max_id)
> > > + return INVALID_IOASID;
> > > +
> > > + if (vcmd_alloc_pasid(iommu, &ioasid))
> > > + return INVALID_IOASID;
> > > +
> > > + return ioasid;
> > > +}
> > > +
> > > +static void intel_ioasid_free(ioasid_t ioasid, void *data)
> > > +{
> > > + struct intel_iommu *iommu = data;
> > > +
> > > + if (!iommu)
> > > + return;
> > > + /*
> > > + * Sanity check the ioasid owner is done at upper layer,
> > > e.g. VFIO
> > > + * We can only free the PASID when all the devices are
> > > unbond.
> > > + */
> > > + if (ioasid_find(NULL, ioasid, NULL)) {
> > > + pr_alert("Cannot free active IOASID %d\n", ioasid);
> > > + return;
> > > + }
> > > + vcmd_free_pasid(iommu, ioasid);
> > > +}
> > > +#endif
> > > +
> > > int __init intel_iommu_init(void)
> > > {
> > > int ret = -ENODEV;
> > > @@ -5020,6 +5061,32 @@ int __init intel_iommu_init(void)
> > > "%s", iommu->name);
> > > iommu_device_set_ops(&iommu->iommu,
> > > &intel_iommu_ops); iommu_device_register(&iommu->iommu);
> > > +#ifdef CONFIG_INTEL_IOMMU_SVM
> > > + if (ecap_vcs(iommu->ecap) &&
> > > vccap_pasid(iommu->vccap)) {
> > > + pr_info("Register custom PASID
> > > allocator\n");
> > > + /*
> > > + * Register a custom ASID allocator if we
> > > are running
> > > + * in a guest, the purpose is to have a
> > > system wide PASID
> > > + * namespace among all PASID users.
> > > + * There can be multiple vIOMMUs in each
> > > guest but only
> > > + * one allocator is active. All vIOMMU
> > > allocators will
> > > + * eventually be calling the same host
> > > allocator.
> > > + */
> > > + iommu->pasid_allocator.alloc =
> > > intel_ioasid_alloc;
> > > + iommu->pasid_allocator.free =
> > > intel_ioasid_free;
> > > + iommu->pasid_allocator.pdata = (void
> > > *)iommu;
> > > + ret =
> > > ioasid_register_allocator(&iommu->pasid_allocator);
> > > + if (ret) {
> > > + pr_warn("Custom PASID allocator
> > > registeration failed\n");
> > > + /*
> > > + * Disable scalable mode on this
> > > IOMMU if there
> > > + * is no custom allocator. Mixing
> > > SM capable vIOMMU
> > > + * and non-SM vIOMMU are not
> > > supported.
> > > + */
> > > + intel_iommu_sm = 0;
> >
> > It's insufficient to disable scalable mode by only clearing
> > intel_iommu_sm. The DMA_RTADDR_SMT bit in root entry has already
> been
> > set. Probably, you need to
> >
> > for each iommu
> > clear DMA_RTADDR_SMT in root entry
> >
> > Alternatively, since vSVA is the only customer of this custom PASID
> > allocator, is it possible to only disable SVA here?
> >
> Yeah, I think disable SVA is better. We can still do gIOVA in SM. I
> guess we need to introduce a flag for sva_enabled.
I'm not sure whether tying above logic to SVA is the right approach.
If vcmd interface doesn't work, the whole SM mode doesn't make
sense which is based on PASID-granular protection (SVA is only one
usage atop). If the only remaining usage of SM is to map gIOVA using
reserved PASID#0, then why not disabling SM and just fallback to
legacy mode?
Based on that I prefer to disabling the SM mode completely (better
through an interface), and move the logic out of CONFIG_INTEL_
IOMMU_SVM
> > > + }
> > > + }
> > > +#endif
> > > }
> > >
> > > bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
> > > diff --git a/include/linux/intel-iommu.h
> > > b/include/linux/intel-iommu.h index 1d4b8dcdc5d8..c624733cb2e6
> > > 100644 --- a/include/linux/intel-iommu.h
> > > +++ b/include/linux/intel-iommu.h
> > > @@ -19,6 +19,7 @@
> > > #include <linux/iommu.h>
> > > #include <linux/io-64-nonatomic-lo-hi.h>
> > > #include <linux/dmar.h>
> > > +#include <linux/ioasid.h>
> > >
> > > #include <asm/cacheflush.h>
> > > #include <asm/iommu.h>
> > > @@ -546,6 +547,7 @@ struct intel_iommu {
> > > #ifdef CONFIG_INTEL_IOMMU_SVM
> > > struct page_req_dsc *prq;
> > > unsigned char prq_name[16]; /* Name for PRQ interrupt
> > > */
> > > + struct ioasid_allocator_ops pasid_allocator; /* Custom
> > > allocator for PASIDs */ #endif
> > > struct q_inval *qi; /* Queued invalidation
> > > info */ u32 *iommu_state; /* Store iommu states between suspend and
> > > resume.*/
> >
> > Best regards,
> > baolu
>
> [Jacob Pan]
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