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Message-ID: <CAAhSdy1zfL2kPM-Le6TZSqS2TU1RkgC+zTbB4y31t8TXwVjhEg@mail.gmail.com>
Date: Sat, 26 Oct 2019 08:52:16 +0530
From: Anup Patel <anup@...infault.org>
To: Paul Walmsley <paul.walmsley@...ive.com>
Cc: Anup Patel <Anup.Patel@....com>,
Palmer Dabbelt <palmer@...ive.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Radim K <rkrcmar@...hat.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Alexander Graf <graf@...zon.com>,
Atish Patra <Atish.Patra@....com>,
Alistair Francis <Alistair.Francis@....com>,
Damien Le Moal <Damien.LeMoal@....com>,
Christoph Hellwig <hch@...radead.org>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v9 00/22] KVM RISC-V Support
On Sat, Oct 26, 2019 at 4:40 AM Paul Walmsley <paul.walmsley@...ive.com> wrote:
>
> Hi Anup,
>
> On Wed, 16 Oct 2019, Anup Patel wrote:
>
> > This series adds initial KVM RISC-V support. Currently, we are able to boot
> > RISC-V 64bit Linux Guests with multiple VCPUs.
> >
> > Few key aspects of KVM RISC-V added by this series are:
> > 1. Minimal possible KVM world-switch which touches only GPRs and few CSRs.
> > 2. Full Guest/VM switch is done via vcpu_get/vcpu_put infrastructure.
> > 3. KVM ONE_REG interface for VCPU register access from user-space.
> > 4. PLIC emulation is done in user-space.
> > 5. Timer and IPI emuation is done in-kernel.
> > 6. MMU notifiers supported.
> > 7. FP lazy save/restore supported.
> > 8. SBI v0.1 emulation for KVM Guest available.
> > 9. Forward unhandled SBI calls to KVM userspace.
> > 10. Hugepage support for Guest/VM
>
> Several patches in this series cause 'checkpatch.pl --strict' to flag
> issues. When you respin this series, could you fix those, please?
I generally run checkpatch.pl every time before sending patches.
I will try checkpatch.pl with --strict parameter as well in v10 series.
Regards,
Anup
>
>
> thanks,
>
> - Paul
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