linux-kernel - Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 28 Oct 2019 12:53:47 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, Taniya Das <tdas@...eaurora.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150

On 27-10-19, 14:25, Stephen Boyd wrote:
> Quoting Vinod Koul (2019-10-21 03:54:35)
> > On 17-10-19, 10:48, Stephen Boyd wrote:
> > > > > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > index 12ca2d14797f..13d4d14a5744 100644
> > > > > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > > > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> > > > > >         },
> > > > > >  };
> > > > > >  
> > > > > > +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> > > > > > +       .halt_check = BRANCH_HALT_SKIP,
> > > > > 
> > > > > Why skip?
> > > > 
> > > > I will explore and add comments for that
> > > > 
> > > > > > +       .clkr = {
> > > > > > +               .enable_reg = 0x52004,
> > > > > > +               .enable_mask = BIT(15),
> > > > > > +               .hw.init = &(struct clk_init_data){
> > > > > > +                       .name = "gcc_gpu_gpll0_clk_src",
> > > > > > +                       .parent_hws = (const struct clk_hw *[]){
> > > > > > +                               &gpll0.clkr.hw },
> > > > > > +                       .num_parents = 1,
> > > > > > +                       .flags = CLK_SET_RATE_PARENT,
> > > > > > +                       .ops = &clk_branch2_ops,
> > > > > > +               },
> > > > > > +       },
> > > > > > +};
> > > > > > +
> > > > > > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> > > > > > +       .halt_check = BRANCH_HALT_SKIP,
> > > > > 
> > > > > Why skip?
> > > > > 
> > > 
> > > Any answer from the explorations?
> > 
> > Yeah so asking around the answer I got is that these are external
> > clocks and we need cannot rely on CLK_OFF bit for these clocks
> > 
> 
> The parents are from some other clk controller? Not external to the
> chip, right? If so, I still don't get it. Please add some sort of
> comment here in the code.


Yeah I have added a comment and posted v2 few days back.

Thanks
-- 
~Vinod