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Message-ID: <20191028155457.5uae2crf3ygvn3qn@localhost>
Date: Mon, 28 Oct 2019 08:54:57 -0700
From: Olof Johansson <olof@...om.net>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: lee.jones@...aro.org, linux-kernel@...r.kernel.org, arm@...nel.org,
Stephan Gerhold <stephan@...hold.net>
Subject: Re: [PATCH v3] mfd: db8500-prcmu: Support U8420-sysclk firmware
On Sat, Oct 26, 2019 at 11:47:32PM +0200, Linus Walleij wrote:
> There is a distinct version of the Ux500 U8420 variant
> with "sysclk", as can be seen from the vendor code that
> didn't make it upstream, this firmware lacks the
> ULPPLL (ultra-low power phase locked loop) which in
> effect means that the timer clock is instead wired to
> the 32768 Hz always-on clock.
>
> This has some repercussions when enabling the timer
> clock as the code as it stands will disable the timer
> clock on these platforms (lacking the so-called
> "doze mode") and obtaining the wrong rate of the timer
> clock.
>
> The timer frequency is of course needed very early in
> the boot, and as a consequence, we need to shuffle
> around the early PRCMU init code: whereas in the past
> we did not need to look up the PRCMU firmware version
> in the early init, but now we need to know the version
> before the core system timers are registered so we
> restructure the platform callbacks to the PRCMU so as
> not to take any arguments and instead look up the
> resources it needs directly from the device tree
> when initializing.
>
> As we do not yet support any platforms using this
> firmware it is not a regression, but as PostmarketOS
> is starting to support products with this firmware we
> need to fix this up.
>
> The low rate of 32kHz also makes the MTU timer unsuitable
> as delay timer but this needs to be fixed in a separate
> patch.
>
> Cc: arm@...nel.org
> Cc: Lee Jones <lee.jones@...aro.org>
> Cc: Stephan Gerhold <stephan@...hold.net>
> Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
Fine with me to go through MTD, so:
Acked-by: Olof Johansson <olof@...om.net>
-Olof
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