linux-kernel - Re: [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1ac70f92-c148-ca88-a2c1-ec90741ac123@linux.intel.com>
Date:   Tue, 29 Oct 2019 14:14:28 +0800
From:   Dilip Kota <eswara.kota@...ux.intel.com>
To:     "andriy.shevchenko@...el.com" <andriy.shevchenko@...el.com>
Cc:     Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>,
        "jingoohan1@...il.com" <jingoohan1@...il.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "andrew.murray@....com" <andrew.murray@....com>,
        "robh@...nel.org" <robh@...nel.org>,
        "martin.blumenstingl@...glemail.com" 
        <martin.blumenstingl@...glemail.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "hch@...radead.org" <hch@...radead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "cheol.yong.kim@...el.com" <cheol.yong.kim@...el.com>,
        "chuanhua.lei@...ux.intel.com" <chuanhua.lei@...ux.intel.com>,
        "qi-ming.wu@...el.com" <qi-ming.wu@...el.com>
Subject: Re: [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver


On 10/22/2019 7:44 PM, andriy.shevchenko@...el.com wrote:
> On Tue, Oct 22, 2019 at 06:18:57PM +0800, Dilip Kota wrote:
>> On 10/21/2019 6:44 PM, Dilip Kota wrote:
>>> On 10/21/2019 4:29 PM, Gustavo Pimentel wrote:
>>>> On Mon, Oct 21, 2019 at 7:39:19, Dilip Kota
>>>> <eswara.kota@...ux.intel.com>
>>>> wrote:
> First of all, it's a good behaviour to avoid way long quoting.
(Sorry for the late reply, I am back today from sick leave.)
Noted. Will take care of it.

>
>>>>> +static void pcie_update_bits(void __iomem *base, u32 mask, u32
>>>>> val, u32 ofs)
>>>>> +{
>>>>> +    u32 orig, tmp;
>>>>> +
>>>>> +    orig = readl(base + ofs);
>>>>> +
>>>>> +    tmp = (orig & ~mask) | (val & mask);
>>>>> +
>>>>> +    if (tmp != orig)
>>>>> +        writel(tmp, base + ofs);
>>>>> +}
>>>> I'd suggest to the a take on FIELD_PREP() and FIELD_GET() and use more
>>>> intuitive names such as new and old, instead of orig and tmp.
>>> Sure, i will update it.
>> I tried using FIELD_PREP and FIELD_GET but it is failing because FIELD_PREP
>> and FIELD_GET
>> are expecting mask should be constant macro. u32 or u32 const are not
>> accepted.
> If you look at bitfield.h carefully you may find in particular
> u32_replace_bits().

Thanks for pointing it.
But, I found bitfields are not contiguous during few function calls, so 
cannot use them here.

Regards,
Dilip

>