Message-ID: <20191029135152.GJ508460@ulmo>
Date:   Tue, 29 Oct 2019 14:51:52 +0100
From:   Thierry Reding <thierry.reding@...il.com>
To:     Dmitry Osipenko <digetx@...il.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Joseph Lo <josephl@...dia.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Stephen Boyd <sboyd@...nel.org>, devicetree@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v10 00/15] memory: tegra: Introduce Tegra30 EMC driver

On Mon, Aug 12, 2019 at 12:00:28AM +0300, Dmitry Osipenko wrote:
> Hello,
> 
> This series introduces driver for the External Memory Controller (EMC)
> found on Tegra30 chips, it controls the external DRAM on the board. The
> purpose of this driver is to program memory timing for external memory on
> the EMC clock rate change. The driver was tested using the ACTMON devfreq
> driver that performs memory frequency scaling based on memory-usage load.
> 
> Changelog:
> 
> v10: - Addressed review comments that were made by Rob Herring to v9 by
>        dropping unnecessary reg descriptions, specifying valid ranges and
>        using boolean type where appropriate in the device-tree patches.
> 
> v9: - Fixed memory corruption bug that was uncovered after introducing
>       some extra optimizations to the devfreq driver that allows CPU
>       to stay longer in the LP2 cpuidle state. The corruption is caused by
>       a very late AUTO-REFRESH re-enabling due to a possible schedule on
>       waiting for clk-change completion, the re-enabling is now a part of
>       "EMC exec-after-clkchange" hardware sequence.
> 
>     - Added "type: object" to T124 MC YAML, that was missed in v8 by accident.
> 
> v8: - Added two new patches:
> 
>         memory: tegra20-emc: Increase handshake timeout
>         memory: tegra20-emc: wait_for_completion_timeout() doesn't return error
> 
>       Turned out that memory-clk handshake may take much more time under
>       some circumstances. The second patch is a minor cleanup. The same
>       changes are also applied to the Terga30 EMC driver addition-patch.
> 
>       The pattern-properties of YAML bindings gained "type: object", for
>       consistency.
> 
> v7: - Addressed review comments that were made by Rob Herring to v6 by
>       removing old Terga30 Memory Controller binding once it's converted
>       to YAML, by using explicit patterns for the sub-nodes and specifying
>       min/max clock rates in the YAML.
> 
>     - Two patches that were added in v6 are removed from the series:
> 
>         clk: tegra20: emc: Add tegra20_clk_emc_on_pllp()
>         ARM: tegra30: cpuidle: Don't enter LP2 on CPU0 when EMC runs off PLLP
> 
>       Because the problem with the PLLP is resolved now, turned out it was
>       a bug in the CPU-suspend code.
> 
>     - The "Introduce Tegra30 EMC driver" patch got a fix for the "Same Freq"
>       bit typo, it's a bit 27 and not 16.
> 
> v6: - Tegra124 Memory Controller binding factored out into standalone
>       binding because it requires to specify MC_EMEM_ARB_MISC1 for EMEM
>       programming, which is not required for Tegra30. This makes the
>       upstream MC registers specification to match downstream exactly,
>       easing porting of boards memory timings configuration to upstream.
> 
>     - Tegra30/124 Memory Controller binding converted to YAML.
> 
>     - Tegra30 External Memory Controller binding now is in YAML format.
> 
>     - Added workaround for hanging during LP2 when EMC runs off PLLP on
>       Tegra30 in this new patches:
> 
>         clk: tegra20: emc: Add tegra20_clk_emc_on_pllp()
>         ARM: tegra30: cpuidle: Don't enter LP2 on CPU0 when EMC runs off PLLP
> 
>     - Added info message to the Tegra20/30 EMC drivers, telling about
>       RAM code and a number of available timings:
> 
>         memory: tegra20-emc: Print a brief info message about the timings
> 
> v5: - Addressed review comments that were made by Thierry Reding to v4 by
>       adding appropriate copyrights to the source code headers and making
>       Tegra30 EMC driver to use common Tegra20 CLK API directly instead
>       of having a dummy-proxy functions specifically for Tegra30.
> 
>     - Addressed review comments that were made by Stephen Boyd to v4 by
>       rewording commit message of the "Add custom EMC clock implementation"
>       patch and adding clarifying comment (to that patch as well) which
>       tells why EMC is a critical clock.
> 
>     - Added suspend-resume to Tegra30 EMC driver to error out if EMC driver
>       is in a "bad state" as it will likely cause a hang on entering suspend.
> 
>     - Dropped patch "tegra20-emc: Replace clk_get_sys with devm_clk_get"
>       because the replaced clocks are actually should be removed altogether
>       in the "Drop setting EMC rate to max on probe" patch and that was
>       missed by an accident.
> 
>     - Added "tegra20-emc: Pre-configure debug register" patch which ensures
>       that inappropriate HW debug features are disabled at a probe time.
>       The same change is also made in the "Introduce Tegra30 EMC driver"
>       patch.
> 
>     - Added ACKs to the patches from Peter De Schrijver that he gave to v4
>       since all of the v5 changes are actually very minor.
> 
> v4: - Addressed review comments that were made by Peter De Schrijver to v3
>       by adding fence_udelay() after writes in the "Add custom EMC clock
>       implementation" patch.
> 
>     - Added two new minor patches:
> 
>         memory: tegra: Ensure timing control debug features are disabled
>         memory: tegra: Consolidate registers definition into one place
> 
>       The first one is needed to ensure that EMC driver will work
>       properly regardless of hardware configuration left after boot.
>       The second patch is just a minor code cleanup.
> 
>     - The "Introduce Tegra30 EMC driver" got also few very minor changes.
>       Now every possible error case is handled, nothing is ignored.
>       The EMC_DBG register is explicitly initialized during probe to be
>       on the safe side.
> 
> v3: - Addressed review comments that were made by Stephen Boyd to v2 by
>       adding explicit typing for the callback variable, by including
>       "clk-provider.h" directly in the code and by dropping __clk_lookup
>       usage where possible.
> 
>     - Added more patches into this series:
> 
>         memory: tegra20-emc: Drop setting EMC rate to max on probe
>         memory: tegra20-emc: Adapt for clock driver changes
>         memory: tegra20-emc: Include io.h instead of iopoll.h
>         memory: tegra20-emc: Replace clk_get_sys with devm_clk_get
> 
>       Initially I was going to include these patches into other patchset,
>       but changed my mind after rearranging things a tad. The "Adapt for
>       clock driver changes" patch is directly related to the clock changes
>       done in the first patch of this series, the rest are minor cleanups
>       that are fine to include here as well.
> 
>     - Added some more words to the commit message of "Add binding for NVIDIA
>       Tegra30 External Memory Controller" patch, clarifying why common DDR
>       timing device-tree form isn't suitable for Tegra30.
> 
>     - The Tegra30 EMC driver now explicitly selects the registers access
>       mode (EMC_DBG mux), not relying on the setting left from bootloader.
> 
> v2: - Added support for changing MC clock diver configuration based on
>       Memory Controller (MC) configuration which is part of the memory
>       timing.
> 
>     - Merged the "Add custom EMC clock implementation" patch into this
>       series because the "Introduce Tegra30 EMC driver" patch directly
>       depends on it. Please note that Tegra20 EMC driver will need to be
>       adapted for the clock changes as well, I'll send out the Tegra20
>       patches after this series will be applied because of some other
>       dependencies (devfreq) and because the temporary breakage won't
>       be critical (driver will just error out on probe).
> 
>     - EMC driver now performs MC configuration validation by checking
>       that the number of MC / EMC timings matches and that the timings
>       rate is the same.
> 
>     - EMC driver now supports timings that want to change the MC clock
>       configuration.
> 
>     - Other minor prettifying changes of the code.
> 
> Dmitry Osipenko (15):
>   clk: tegra20/30: Add custom EMC clock implementation
>   memory: tegra20-emc: Drop setting EMC rate to max on probe
>   memory: tegra20-emc: Adapt for clock driver changes
>   memory: tegra20-emc: Include io.h instead of iopoll.h
>   memory: tegra20-emc: Pre-configure debug register
>   memory: tegra20-emc: Print a brief info message about the timings
>   memory: tegra20-emc: Increase handshake timeout
>   memory: tegra20-emc: wait_for_completion_timeout() doesn't return
>     error
>   dt-bindings: memory: tegra30: Convert to Tegra124 YAML
>   dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
>   dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory
>     Controller
>   memory: tegra: Introduce Tegra30 EMC driver
>   memory: tegra: Ensure timing control debug features are disabled
>   memory: tegra: Consolidate registers definition into common header
>   ARM: dts: tegra30: Add External Memory Controller node

Applied these to for-5.5/clk, for-5.5/dt-bindings, for-5.5/memory and
for-5.5/arm/dt, thanks.

Thierry

Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)

Powered by blists - more mailing lists