linux-kernel - Re: [PATCH] pinctrl: at91: Enable slewrate by default on SAM9X60

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Message-ID: <CAL_JsqLuPb357uaiyR3N0QOBkcfXOAm57VbWbhaC=90aFmUVkg@mail.gmail.com>
Date:   Wed, 30 Oct 2019 08:15:22 -0500
From:   Rob Herring <robh@...nel.org>
To:     Ludovic Desroches <ludovic.desroches@...rochip.com>
Cc:     Codrin Ciubotariu <codrin.ciubotariu@...rochip.com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org,
        Linus Walleij <linus.walleij@...aro.org>,
        Nicolas Ferre <nicolas.ferre@...rochip.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH] pinctrl: at91: Enable slewrate by default on SAM9X60

On Wed, Oct 30, 2019 at 3:53 AM Ludovic Desroches
<ludovic.desroches@...rochip.com> wrote:
>
> On Tue, Oct 29, 2019 at 04:37:57PM -0500, Rob Herring wrote:
> > On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote:
> > > On SAM9X60, slewrate should be enabled on pins with a switching frequency
> > > below 50Mhz. Since most of our pins do not exceed this value, we enable
> > > slewrate by default. Pins with a switching value that exceeds 50Mhz will
> > > have to explicitly disable slewrate.
> > >
> > > Suggested-by: Ludovic Desroches <ludovic.desroches@...rochip.com>
> > > Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@...rochip.com>
> > > ---
> > >  drivers/pinctrl/pinctrl-at91.c     | 4 ++--
> > >  include/dt-bindings/pinctrl/at91.h | 4 ++--
> > >  2 files changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> > > index 117075b5798f..c135149e84e9 100644
> > > --- a/drivers/pinctrl/pinctrl-at91.c
> > > +++ b/drivers/pinctrl/pinctrl-at91.c
> > > @@ -85,8 +85,8 @@ enum drive_strength_bit {
> > >                                      DRIVE_STRENGTH_SHIFT)
> > >
> > >  enum slewrate_bit {
> > > -   SLEWRATE_BIT_DIS,
> > >     SLEWRATE_BIT_ENA,
> > > +   SLEWRATE_BIT_DIS,
> > >  };
> > >
> > >  #define SLEWRATE_BIT_MSK(name)             (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
> > > @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
> > >  {
> > >     unsigned int tmp;
> > >
> > > -   if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
> > > +   if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
> > >             return;
> > >
> > >     tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
> > > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
> > > index 3831f91fb3ba..e8e117306b1b 100644
> > > --- a/include/dt-bindings/pinctrl/at91.h
> > > +++ b/include/dt-bindings/pinctrl/at91.h
> > > @@ -27,8 +27,8 @@
> > >  #define AT91_PINCTRL_DRIVE_STRENGTH_MED                    (0x2 << 5)
> > >  #define AT91_PINCTRL_DRIVE_STRENGTH_HI                     (0x3 << 5)
> > >
> > > -#define AT91_PINCTRL_SLEWRATE_DIS  (0x0 << 9)
> > > -#define AT91_PINCTRL_SLEWRATE_ENA  (0x1 << 9)
> > > +#define AT91_PINCTRL_SLEWRATE_ENA  (0x0 << 9)
> > > +#define AT91_PINCTRL_SLEWRATE_DIS  (0x1 << 9)
> >
> > This is an ABI. You can't just change the definition.
>
> There is no DT using these definitions. They have been introduced for our new
> SoC but its DT is not submitted yet. I assume it's not too late to do this
> change as nothing will be broken.

Okay, then state this in the commit message.

Rob