linux-kernel - RE: [PATCH v1 2/8] KVM: x86: PEBS output to Intel PT MSRs emulation

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Message-ID: <82D7661F83C1A047AF7DC287873BF1E173835B2F@SHSMSX104.ccr.corp.intel.com>
Date:   Wed, 30 Oct 2019 04:06:49 +0000
From:   "Kang, Luwei" <luwei.kang@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
CC:     "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "rkrcmar@...hat.com" <rkrcmar@...hat.com>,
        "Christopherson, Sean J" <sean.j.christopherson@...el.com>,
        "vkuznets@...hat.com" <vkuznets@...hat.com>,
        "wanpengli@...cent.com" <wanpengli@...cent.com>,
        "jmattson@...gle.com" <jmattson@...gle.com>,
        "joro@...tes.org" <joro@...tes.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>, "hpa@...or.com" <hpa@...or.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>,
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        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
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        "namhyung@...nel.org" <namhyung@...nel.org>
Subject: RE: [PATCH v1 2/8] KVM: x86: PEBS output to Intel PT MSRs emulation

> > Intel new hardware introduces a mechanism to direct PEBS records
> > output into the Intel PT buffer that can be used for enabling PEBS in
> > KVM guest. This patch implements the registers read and write
> > emulation when PEBS is supported in KVM guest.
> >
> > KMM needs to reprogram the counters when the value of these MSRs be
> > changed that to make sure it can take effect in hardware.
> >
> > Signed-off-by: Luwei Kang <luwei.kang@...el.com>
> > ---
> >  arch/x86/include/asm/kvm_host.h  |  4 +++
> > arch/x86/include/asm/msr-index.h |  6 ++++
> > arch/x86/kvm/vmx/capabilities.h  | 15 ++++++++++
> >  arch/x86/kvm/vmx/pmu_intel.c     | 63 ++++++++++++++++++++++++++++++++++++++--
> >  4 files changed, 86 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/msr-index.h
> > b/arch/x86/include/asm/msr-index.h
> > index 20ce682..d22f8d9 100644
> > --- a/arch/x86/include/asm/msr-index.h
> > +++ b/arch/x86/include/asm/msr-index.h
> > @@ -131,9 +131,13 @@
> >  #define LBR_INFO_ABORT			BIT_ULL(61)
> >  #define LBR_INFO_CYCLES			0xffff
> >
> > +#define MSR_IA32_PEBS_PMI_AFTER_REC	BIT_ULL(60)
> > +#define MSR_IA32_PEBS_OUTPUT_PT		BIT_ULL(61)
> > +#define MSR_IA32_PEBS_OUTPUT_MASK	(3ULL << 61)
> >  #define MSR_IA32_PEBS_ENABLE		0x000003f1
> >  #define MSR_PEBS_DATA_CFG		0x000003f2
> >  #define MSR_IA32_DS_AREA		0x00000600
> > +#define MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT	BIT_ULL(16)
> >  #define MSR_IA32_PERF_CAPABILITIES	0x00000345
> >  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
> >
> > @@ -665,6 +669,8 @@
> >  #define MSR_IA32_MISC_ENABLE_FERR			(1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
> >  #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT		10
> >  #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX		(1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
> > +#define MSR_IA32_MISC_ENABLE_PEBS_BIT			12
> > +#define MSR_IA32_MISC_ENABLE_PEBS			(1ULL << MSR_IA32_MISC_ENABLE_PEBS_BIT)
> >  #define MSR_IA32_MISC_ENABLE_TM2_BIT			13
> >  #define MSR_IA32_MISC_ENABLE_TM2			(1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
> >  #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT	19
> 
> Some of these already exist but are local to perf. Don't blindly introduce more without unifying.

Got it. Will reuse the exist definition in perf.

Thanks,
Luwei Kang