linux-kernel - Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery

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Date:   Thu, 31 Oct 2019 20:02:24 +0800
From:   Zenghui Yu <yuzenghui@...wei.com>
To:     Marc Zyngier <maz@...nel.org>, <kvmarm@...ts.cs.columbia.edu>,
        <linux-kernel@...r.kernel.org>
CC:     Eric Auger <eric.auger@...hat.com>,
        James Morse <james.morse@....com>,
        Julien Thierry <julien.thierry.kdev@...il.com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        "Andrew Murray" <Andrew.Murray@....com>,
        Jayachandran C <jnair@...vell.com>,
        "Robert Richter" <rrichter@...vell.com>
Subject: Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery

Hi Marc,

On 2019/10/27 22:42, Marc Zyngier wrote:
> While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller
> implementations to be built. Add the required glue to dynamically
> compute the limit.
> 
> Signed-off-by: Marc Zyngier <maz@...nel.org>
> ---
>   drivers/irqchip/irq-gic-v3-its.c   | 11 ++++++++++-
>   drivers/irqchip/irq-gic-v3.c       |  3 +++
>   include/linux/irqchip/arm-gic-v3.h |  5 +++++
>   3 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 94c9c2e9f917..40912b3fb0e1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -121,7 +121,16 @@ struct its_node {
>   #define ITS_ITT_ALIGN		SZ_256
>   
>   /* The maximum number of VPEID bits supported by VLPI commands */
> -#define ITS_MAX_VPEID_BITS	(16)
> +#define ITS_MAX_VPEID_BITS						\
> +	({								\
> +		int nvpeid = 16;					\
> +		if (gic_rdists->has_rvpeid &&				\
> +		    gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)		\
> +			nvpeid = 1 + (gic_rdists->gicd_typer2 &		\
> +				      GICD_TYPER2_VID);			\

Does it make sense to let nvpeid not more than 16 here? As the spec says
"Values above 0x0F are RESERVED". But I don't know why should we have
this restriction ;-)

Either way,

Reviewed-by: Zenghui Yu <yuzenghui@...wei.com>


Thanks

> +									\
> +		nvpeid;							\
> +	})
>   #define ITS_MAX_VPEID		(1 << (ITS_MAX_VPEID_BITS))
>   
>   /* Convert page order to size in bytes */
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 4f20caf9bc88..50538709bd49 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -1556,6 +1556,9 @@ static int __init gic_init_bases(void __iomem *dist_base,
>   
>   	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
>   	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
> +
> +	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
> +
>   	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
>   						 &gic_data);
>   	irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index c98f34296599..8c6be56da7e9 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -13,6 +13,7 @@
>   #define GICD_CTLR			0x0000
>   #define GICD_TYPER			0x0004
>   #define GICD_IIDR			0x0008
> +#define GICD_TYPER2			0x000C
>   #define GICD_STATUSR			0x0010
>   #define GICD_SETSPI_NSR			0x0040
>   #define GICD_CLRSPI_NSR			0x0048
> @@ -89,6 +90,9 @@
>   #define GICD_TYPER_ESPIS(typer)						\
>   	(((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
>   
> +#define GICD_TYPER2_VIL			(1U << 7)
> +#define GICD_TYPER2_VID			GENMASK(4, 0)
> +
>   #define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
>   #define GICD_IROUTER_SPI_MODE_ANY	(1U << 31)
>   
> @@ -613,6 +617,7 @@ struct rdists {
>   	void			*prop_table_va;
>   	u64			flags;
>   	u32			gicd_typer;
> +	u32			gicd_typer2;
>   	bool			has_vlpis;
>   	bool			has_rvpeid;
>   	bool			has_direct_lpi;
>