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Message-ID: <86eeyry6hq.wl-maz@kernel.org>
Date: Fri, 01 Nov 2019 15:13:37 +0000
From: Marc Zyngier <maz@...nel.org>
To: Zenghui Yu <yuzenghui@...wei.com>
Cc: <kvmarm@...ts.cs.columbia.edu>, <linux-kernel@...r.kernel.org>,
Eric Auger <eric.auger@...hat.com>,
James Morse <james.morse@....com>,
Julien Thierry <julien.thierry.kdev@...il.com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
"Andrew Murray" <Andrew.Murray@....com>,
Jayachandran C <jnair@...vell.com>,
"Robert Richter" <rrichter@...vell.com>
Subject: Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery
On Thu, 31 Oct 2019 12:02:24 +0000,
Zenghui Yu <yuzenghui@...wei.com> wrote:
>
> Hi Marc,
>
> On 2019/10/27 22:42, Marc Zyngier wrote:
> > While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller
> > implementations to be built. Add the required glue to dynamically
> > compute the limit.
> >
> > Signed-off-by: Marc Zyngier <maz@...nel.org>
> > ---
> > drivers/irqchip/irq-gic-v3-its.c | 11 ++++++++++-
> > drivers/irqchip/irq-gic-v3.c | 3 +++
> > include/linux/irqchip/arm-gic-v3.h | 5 +++++
> > 3 files changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> > index 94c9c2e9f917..40912b3fb0e1 100644
> > --- a/drivers/irqchip/irq-gic-v3-its.c
> > +++ b/drivers/irqchip/irq-gic-v3-its.c
> > @@ -121,7 +121,16 @@ struct its_node {
> > #define ITS_ITT_ALIGN SZ_256
> > /* The maximum number of VPEID bits supported by VLPI commands
> > */
> > -#define ITS_MAX_VPEID_BITS (16)
> > +#define ITS_MAX_VPEID_BITS \
> > + ({ \
> > + int nvpeid = 16; \
> > + if (gic_rdists->has_rvpeid && \
> > + gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
> > + nvpeid = 1 + (gic_rdists->gicd_typer2 & \
> > + GICD_TYPER2_VID); \
>
> Does it make sense to let nvpeid not more than 16 here? As the spec says
> "Values above 0x0F are RESERVED". But I don't know why should we have
> this restriction ;-)
This is something that Andrew raised in the previous version. My take
on this is that properly implemented HW should give us something that
matches the spec (in the 0-15 range), and I don't think that guarding
against that is useful at this stage.
My understanding is that once the architecture allows using the 16-31
range, we'll either use it directly because it is just a natural
extension to the existing range, or they mean something different
altogether and we'll get a new discovery bit somewhere.
> Either way,
>
> Reviewed-by: Zenghui Yu <yuzenghui@...wei.com>
Thanks,
M.
--
Jazz is not dead, it just smells funny.
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