linux-kernel - Re: [PATCH v5 4/6] powerpc: Convert flush_icache

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Message-ID: <201911041239.EsFtgq96%lkp@intel.com>
Date:   Mon, 4 Nov 2019 12:54:59 +0800
From:   kbuild test robot <lkp@...el.com>
To:     Alastair D'Silva <alastair@....ibm.com>
Cc:     kbuild-all@...ts.01.org, alastair@...ilva.org,
        Christophe Leroy <christophe.leroy@....fr>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        Allison Randal <allison@...utok.net>, Qian Cai <cai@....pw>,
        Thomas Gleixner <tglx@...utronix.de>,
        Nicholas Piggin <npiggin@...il.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        David Hildenbrand <david@...hat.com>,
        linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 4/6] powerpc: Convert flush_icache_range & friends to C

Hi Alastair,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.4-rc6 next-20191031]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Alastair-D-Silva/powerpc-convert-cache-asm-to-C/20191104-103528
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allnoconfig (attached as .config)
compiler: powerpc-linux-gcc (GCC) 7.4.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.4.0 make.cross ARCH=powerpc 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@...el.com>

All errors (new ones prefixed by >>):

   arch/powerpc/mm/mem.c: In function 'flush_dcache_icache_page':
>> arch/powerpc/mm/mem.c:469:29: error: passing argument 1 of 'flush_coherent_icache' makes integer from pointer without a cast [-Werror=int-conversion]
      if (flush_coherent_icache((void *)addr))
                                ^
   arch/powerpc/mm/mem.c:326:20: note: expected 'long unsigned int' but argument is of type 'void *'
    static inline bool flush_coherent_icache(unsigned long addr)
                       ^~~~~~~~~~~~~~~~~~~~~
   arch/powerpc/mm/mem.c: In function '__flush_dcache_icache':
>> arch/powerpc/mm/mem.c:486:13: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
     u64 addr = (u64)page;
                ^
   cc1: all warnings being treated as errors

vim +/flush_coherent_icache +469 arch/powerpc/mm/mem.c

   449	
   450	void flush_dcache_icache_page(struct page *page)
   451	{
   452	#ifdef CONFIG_HUGETLB_PAGE
   453		if (PageCompound(page)) {
   454			flush_dcache_icache_hugepage(page);
   455			return;
   456		}
   457	#endif
   458	#if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
   459		/* On 8xx there is no need to kmap since highmem is not supported */
   460		__flush_dcache_icache(page_address(page));
   461	#else
   462		if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
   463			void *start = kmap_atomic(page);
   464			__flush_dcache_icache(start);
   465			kunmap_atomic(start);
   466		} else {
   467			unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
   468	
 > 469			if (flush_coherent_icache((void *)addr))
   470				return;
   471			flush_dcache_icache_phys(addr);
   472		}
   473	#endif
   474	}
   475	EXPORT_SYMBOL(flush_dcache_icache_page);
   476	
   477	/**
   478	 * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
   479	 * Note: this is necessary because the instruction cache does *not*
   480	 * snoop from the data cache.
   481	 *
   482	 * @page: the address of the page to flush
   483	 */
   484	void __flush_dcache_icache(void *page)
   485	{
 > 486		u64 addr = (u64)page;
   487	
   488		if (flush_coherent_icache(addr))
   489			return;
   490	
   491		clean_dcache_range(addr, addr + PAGE_SIZE);
   492	
   493		/*
   494		 * We don't flush the icache on 44x. Those have a virtual icache and we
   495		 * don't have access to the virtual address here (it's not the page
   496		 * vaddr but where it's mapped in user space). The flushing of the
   497		 * icache on these is handled elsewhere, when a change in the address
   498		 * space occurs, before returning to user space.
   499		 */
   500	
   501		if (cpu_has_feature(MMU_FTR_TYPE_44x))
   502			return;
   503	
   504		invalidate_icache_range(addr, addr + PAGE_SIZE);
   505	}
   506	EXPORT_SYMBOL(__flush_dcache_icache);
   507	

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