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Message-ID: <4a8801c0-97a3-69f9-abf7-4a74c90d40a3@codeaurora.org>
Date: Mon, 4 Nov 2019 11:40:18 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: Stephen Boyd <swboyd@...omium.org>, kgunda@...eaurora.org
Cc: agross@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, mka@...omium.org
Subject: Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter
device
On 10/30/2019 8:07 PM, Stephen Boyd wrote:
> Quoting kgunda@...eaurora.org (2019-10-29 23:06:43)
>> On 2019-10-29 22:11, Stephen Boyd wrote:
>>> Quoting Rajendra Nayak (2019-10-23 02:02:15)
>>>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> index 04808a07d7da..6584ac6e6c7b 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> @@ -224,6 +224,25 @@
>>>> };
>>>> };
>>>>
>>>> + spmi_bus: spmi@...0000 {
>>>> + compatible = "qcom,spmi-pmic-arb";
>>>> + reg = <0 0xc440000 0 0x1100>,
>>>
>>> Please pad out the registers to 8 numbers. See sdm845.
>> Ok.. Will address it in the next series.
>>>
>>>> + <0 0xc600000 0 0x2000000>,
>>>> + <0 0xe600000 0 0x100000>,
>>>> + <0 0xe700000 0 0xa0000>,
>>>> + <0 0xc40a000 0 0x26000>;
>>>> + reg-names = "core", "chnls", "obsrvr", "intr",
>>>> "cnfg";
>>>> + interrupt-names = "periph_irq";
>>>> + interrupts-extended = <&pdc 1
>>>> IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> This is different than sdm845. I guess pdc is working?
>>>
>> Yes. For SDM845 pdc controller support was not yet added. That's why
>> still the GIC interrupt is used.
>> Where as for SC7180 the same is added with
>> https://lore.kernel.org/patchwork/patch/1143335/.
>>
>> Yes. pdc is working.
>
> Cool. The patch that adds pdc to the DT should come before this one
> then. In reality, it would be better if it was all squashed down into
> one big commit that just introduces the SoC file and one commit for
> PMICs and then one commit for the idp board. Then we don't have this
> ordering problem.
I'll fix the ordering issues when I respin.
I could squash all of the patches touching the SoC dtsi, but given the
authorship for each varies, I will keep it as is perhaps.
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