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Message-ID: <20191104092252.GS2695@vkoul-mobl.Dlink>
Date: Mon, 4 Nov 2019 14:52:52 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 5/5] phy: qcom: qmp: Add SDM845 QHP PCIe PHY
On 03-11-19, 20:47, Bjorn Andersson wrote:
> On Sun 03 Nov 01:21 PDT 2019, Vinod Koul wrote:
> > On 01-11-19, 17:16, Bjorn Andersson wrote:
> [..]
> > > +/* PCIE GEN3 COM registers */
> > > +#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
> >
> > No QPHY_ tag with these?
>
> These are the actual register names from the hardware specification, do
> you foresee any issues with naming them like this?
It would make them consistent, rest of the registers do have that.
>
> > > +#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
> >
> > Can we sort these please!
> >
>
> Yes, that sounds reasonable. I'll respin with these sorted by address.
Great, thanks
--
~Vinod
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