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Message-ID: <20191105212941.GA8677@bogus>
Date: Tue, 5 Nov 2019 15:29:41 -0600
From: Rob Herring <robh@...nel.org>
To: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
Cc: linus.walleij@...aro.org, mark.rutland@....com,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, andriy.shevchenko@...el.com,
qi-ming.wu@...el.com, yixin.zhu@...ux.intel.com,
cheol.yong.kim@...el.com
Subject: Re: [PATCH v3 2/2] dt-bindings: pinctrl: intel: Add for new SoC
On Tue, Nov 05, 2019 at 02:49:43PM +0800, Rahul Tanwar wrote:
> Add dt bindings document for pinmux & GPIO controller driver of
> Intel Lightning Mountain SoC.
>
> Signed-off-by: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
> ---
> .../bindings/pinctrl/intel,lgm-pinctrl.yaml | 114 +++++++++++++++++++++
> 1 file changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
> new file mode 100644
> index 000000000000..961ac877a962
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
> @@ -0,0 +1,114 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
> +
> +maintainers:
> + - Rahul Tanwar <rahul.tanwar@...ux.intel.com>
> +
> +description: |
> + Pinmux & GPIO controller controls pin multiplexing & configuration including
> + GPIO function selection & GPIO attributes configuration.
> +
> + Please refer to [1] for details of the common pinctrl bindings used by the
> + client devices.
> +
> + [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> +properties:
> + compatible:
> + const: intel,lgm-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> +# Client device subnode's properties
> +patternProperties:
> + "^.*@[0-9a-fA-F]+$":
A unit address is wrong here. Please define some pattern we can match
on. '-pins$' perhaps.
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> +
> + properties:
> + function:
> + $ref: /schemas/types.yaml#/definitions/string
> + description:
> + A string containing the name of the function to mux to the group.
> +
> + groups:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description:
> + An array of strings identifying the list of groups.
> +
> + pins:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description:
> + List of pins to select with this function.
> +
> + pinmux:
> + description: The applicable mux group.
> + allOf:
> + - $ref: "/schemas/types.yaml#/definitions/uint32"
> + - enum:
> + - 0 #PINMUX_GPIO
> + - 1
> + - 2
> + - 3
> + - 4
> +
> + bias-pull-up:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Specifies pull-up configuration.
Isn't this boolean?
> +
> + bias-pull-down:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Specifies pull-down configuration.
And this?
Though looks like sometimes it has a value? Pull strength I guess.
> +
> + drive-strength:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Enables driver-current.
> +
> + slew-rate:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Enables slew-rate.
> +
> + drive-open-drain:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Specifies open-drain configuration.
boolean?
> +
> + output-enable:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Specifies if the pin is to be configured as output.
boolean?
But really, all of these should have a common schema defining the types
and only put any additional constraints here.
> +
> +
> + required:
> + - function
> + - groups
> +
> +required:
> + - compatible
> + - reg
additionalProperties: false
> +
> +examples:
> + # Pinmux controller node
> + - |
> + pinctrl: pinctrl@...80000 {
> + compatible = "intel,lgm-pinctrl";
> + reg = <0xe2880000 0x100000>;
> +
> + # Client device subnode
> + uart0:uart0 {
space ^
> + pins = <64>, /* UART_RX0 */
> + <65>; /* UART_TX0 */
> + function = "CONSOLE_UART0";
> + pinmux = <1>,
> + <1>;
> + groups = "CONSOLE_UART0";
> + };
> + };
> +
> +...
> --
> 2.11.0
>
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