linux-kernel - Re: [PATCH v2 1/2] dt-bindings: PCI: designware: Add binding for ZRX-DC PHY property

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 5 Nov 2019 15:53:32 -0600
From:   Rob Herring <robh@...nel.org>
To:     Anvesh Salveru <anvesh.s@...sung.com>
Cc:     linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, bhelgaas@...gle.com,
        gustavo.pimentel@...opsys.com, jingoohan1@...il.com,
        pankaj.dubey@...sung.com, Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: designware: Add binding for
 ZRX-DC PHY property

On Mon, Oct 28, 2019 at 05:46:27PM +0530, Anvesh Salveru wrote:
> Add support for ZRX-DC compliant PHYs. If PHY is not compliant to ZRX-DC
> specification, then after every 100ms link should transition to recovery
> state during the low power states which increases power consumption.
> 
> Platforms with ZRX-DC compliant PHY can use "snps,phy-zrxdc-compliant"
> property in DesignWare controller DT node.
> 
> CC: Rob Herring <robh+dt@...nel.org>
> CC: Mark Rutland <mark.rutland@....com>
> Signed-off-by: Anvesh Salveru <anvesh.s@...sung.com>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@...sung.com>
> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
> ---
> Change in v2: None
> 
>  Documentation/devicetree/bindings/pci/designware-pcie.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> index 78494c4050f7..9507ac38ac89 100644
> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> @@ -38,6 +38,8 @@ Optional properties:
>     for data corruption. CDM registers include standard PCIe configuration
>     space registers, Port Logic registers, DMA and iATU (internal Address
>     Translation Unit) registers.
> +- snps,phy-zrxdc-compliant: This property is needed if phy complies with the
> +  ZRX-DC specification.

If this is a property of the phy, then it belongs in the phy node or 
should just be implied by the phy's compatible. IOW, you should be able 
to support this or not without changing DTs.

Is this spec Synopys specific? (About the only thing Google turns up are 
your patches.) If not, then probably shouldn't have a 'snps' prefix.

>  RC mode:
>  - num-viewport: number of view ports configured in hardware. If a platform
>    does not specify it, the driver assumes 2.
> -- 
> 2.17.1
>