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Message-Id: <20191106193609.19645-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Wed, 6 Nov 2019 19:36:07 +0000
From: Lad Prabhakar <prabhakar.csengg@...il.com>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Kishon Vijay Abraham I <kishon@...com>,
Marek Vasut <marek.vasut+renesas@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
linux-pci@...r.kernel.org
Cc: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Andrew Murray <andrew.murray@....com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-renesas-soc@...r.kernel.org,
Chris Paterson <Chris.Paterson2@...esas.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 3/5] PCI: rcar: Add R-Car PCIe endpoint device tree bindings
From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>
This patch adds the bindings for the R-Car PCIe endpoint driver.
Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
.../devicetree/bindings/pci/rcar-pci-ep.txt | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt
new file mode 100644
index 000000000000..b8c8616ca007
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt
@@ -0,0 +1,43 @@
+* Renesas R-Car PCIe Endpoint Controller DT description
+
+Required properties:
+ "renesas,pcie-ep-r8a774c0" for the R8A774C0 SoC;
+ "renesas,pcie-ep-rcar-gen3" for a generic R-Car Gen3 or
+ RZ/G2 compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: Five register ranges as listed in the reg-names property
+- reg-names: Must include the following names
+ - "apb-base"
+ - "memory0"
+ - "memory1"
+ - "memory2"
+ - "memory3"
+- resets: Must contain phandles to PCIe-related reset lines exposed by IP block
+- clocks: from common clock binding: clock specifiers for the PCIe controller
+ clock.
+- clock-names: from common clock binding: should be "pcie".
+
+Optional Property:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+Example:
+
+SoC-specific DT Entry:
+
+ pcie_ep: pcie_ep@...00000 {
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ };
--
2.20.1
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