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Message-ID: <DM6PR12MB4010413DC722963F00461666DA790@DM6PR12MB4010.namprd12.prod.outlook.com>
Date: Wed, 6 Nov 2019 09:43:11 +0000
From: Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
To: Dilip Kota <eswara.kota@...ux.intel.com>,
"gustavo.pimentel@...opsys.com" <Gustavo.Pimentel@...opsys.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"andrew.murray@....com" <andrew.murray@....com>,
"helgaas@...nel.org" <helgaas@...nel.org>,
"jingoohan1@...il.com" <jingoohan1@...il.com>,
"robh@...nel.org" <robh@...nel.org>,
"martin.blumenstingl@...glemail.com"
<martin.blumenstingl@...glemail.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"andriy.shevchenko@...el.com" <andriy.shevchenko@...el.com>,
"cheol.yong.kim@...el.com" <cheol.yong.kim@...el.com>,
"chuanhua.lei@...ux.intel.com" <chuanhua.lei@...ux.intel.com>,
"qi-ming.wu@...el.com" <qi-ming.wu@...el.com>
Subject: RE: [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper
function
On Wed, Nov 6, 2019 at 3:44:3, Dilip Kota <eswara.kota@...ux.intel.com>
wrote:
> Utilize DesugnWare helper functions to configure Fast Training
> Sequence. Drop the respective code in the driver.
Please fix
s/DesugnWare/DesignWare
>
> Signed-off-by: Dilip Kota <eswara.kota@...ux.intel.com>
> ---
> drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index d00252bd8fae..02d93b8c7942 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
> #define ACK_N_FTS_MASK GENMASK(15, 8)
> #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
>
> -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
> -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
> -
> /* ARTPEC-6 specific registers */
> #define PCIECFG 0x18
> #define PCIECFG_DBG_OEN BIT(24)
> @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
> * Set the Number of Fast Training Sequences that the core
> * advertises as its N_FTS during Gen2 or Gen3 link training.
> */
> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> - val &= ~FAST_TRAINING_SEQ_MASK;
> - val |= FAST_TRAINING_SEQ(180);
> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> + dw_pcie_link_set_n_fts(pci, 180);
> }
>
> static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
> --
> 2.11.0
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