linux-kernel - Re: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller

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Message-ID: <2dcc3fca914a454006bcf2e9bd4479a30228e9fa.camel@suse.de>
Date:   Thu, 07 Nov 2019 19:24:03 +0100
From:   Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
To:     Stefan Wahren <wahrenst@....net>,
        Andrew Murray <andrew.murray@....com>,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        bcm-kernel-feedback-list@...adcom.com,
        linux-rpi-kernel@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Eric Anholt <eric@...olt.net>
Cc:     f.fainelli@...il.com, phil@...pberrypi.org,
        linux-kernel@...r.kernel.org, mbrugger@...e.com,
        james.quinlan@...adcom.com
Subject: Re: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller

On Thu, 2019-11-07 at 18:44 +0100, Stefan Wahren wrote:
> Hi Nicolas,
> 
> please move this patch behind the driver patches, which is the better order.
> 
> Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> > This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
> > XHCI USB 3.0 controller.
> AFAIU this only applies to the Raspberry Pi 4, since the VIA is outside
> of the SoC.
> > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> > ---
> >  arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
> >  1 file changed, 47 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> > index a9d84e28f245..c7b2e7b57da6 100644
> > --- a/arch/arm/boot/dts/bcm2711.dtsi
> > +++ b/arch/arm/boot/dts/bcm2711.dtsi
> > @@ -288,6 +288,53 @@
> >  		arm,cpu-registers-not-fw-configured;
> >  	};
> > 
> > +	scb {
> > +		compatible = "simple-bus";
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +
> > +		ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
> > +			 <0x6 0x00000000  0x6 0x00000000  0x40000000>;
> > +
> > +		pcie_0: pcie@...00000 {
> > +			compatible = "brcm,bcm2711-pcie";
> > +			reg = <0x0 0x7d500000 0x9310>;
> > +			msi-controller;
> > +			msi-parent = <&pcie_0>;
> > +			#address-cells = <3>;
> > +			#interrupt-cells = <1>;
> > +			#size-cells = <2>;
> > +			linux,pci-domain = <0>;
> > +			brcm,enable-ssc;
> > +			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "pcie", "msi";
> > +			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > +			interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> > +							IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 2 &gicv2 GIC_SPI 144
> > +							IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 3 &gicv2 GIC_SPI 145
> > +							IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 4 &gicv2 GIC_SPI 146
> > +							IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +			ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> > +				  0x0 0x04000000>;
> > +			/*
> > +			 * The wrapper around the PCIe block has a bug
> > +			 * preventing it from accessing beyond the first 3GB of
> > +			 * memory. As the bus DMA mask is rounded up to the
> > +			 * closest power of two of the dma-range size, we're
> > +			 * forced to set the limit at 2GB. This can be
> > +			 * harmlessly changed in the future once the DMA code
> > +			 * handles non power of two DMA limits.
> > +			 */
> > +			dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> > +				      0x0 0x80000000>;
> In case this bug will ever be fixed, do you see this as a future proof
> practical solution?

The dts I provide should work on any bcm2711 (fixed or not) and any future
kernel, with the downside that we'll perform some unnecessary buffer bouncing.

If we were able to address the whole 32bit address space on some future bcm2711
we'd be forced to update the dma-ranges in the bootloader based on the SoC
revision.

The driver should work with any sensible dma-range, I even did a test emulating
the 4GB inbound memory setup.

Regards,
Nicolas


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