linux-kernel - [PATCH] clk: zynqmp: Correct bit index for divider flag

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Message-Id: <1573117290-7990-1-git-send-email-rajan.vaja@xilinx.com>
Date:   Thu,  7 Nov 2019 01:01:30 -0800
From:   Rajan Vaja <rajan.vaja@...inx.com>
To:     mturquette@...libre.com, sboyd@...nel.org, michal.simek@...inx.com,
        m.tretter@...gutronix.de, jollys@...inx.com
Cc:     linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Rajan Vaja <rajan.vaja@...inx.com>,
        Jolly Shah <jolly.shah@...inx.com>
Subject: [PATCH] clk: zynqmp: Correct bit index for divider flag

Update divider flag bit index to match with firmware.

Signed-off-by: Rajan Vaja <rajan.vaja@...inx.com>
Signed-off-by: Jolly Shah <jolly.shah@...inx.com>
Signed-off-by: Michal Simek <michal.simek@...inx.com>
---
 drivers/clk/zynqmp/divider.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..9e60834 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
 /*
  * Zynq UltraScale+ MPSoC Divider support
  *
- *  Copyright (C) 2016-2018 Xilinx
+ *  Copyright (C) 2016-2019 Xilinx
  *
  * Adjustable divider clock implementation
  */
@@ -25,7 +25,7 @@
 #define to_zynqmp_clk_divider(_hw)		\
 	container_of(_hw, struct zynqmp_clk_divider, hw)
 
-#define CLK_FRAC	BIT(13) /* has a fractional parent */
+#define CLK_FRAC	BIT(8) /* has a fractional parent */
 
 /**
  * struct zynqmp_clk_divider - adjustable divider clock
-- 
2.7.4