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Message-ID: <CAJsYDV+M4kH5aCcJxxLB7UMhT7VsRXJW+RYcykHMTZW+1ftC9w@mail.gmail.com>
Date: Thu, 7 Nov 2019 17:25:32 +0800
From: Chuanhong Guo <gch981213@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: linux-mtd@...ts.infradead.org,
David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] dt-bindings: mtd: mtk-quadspi: update bindings for
mmap flash read
Hi!
On Thu, Nov 7, 2019 at 9:09 AM Rob Herring <robh@...nel.org> wrote:
>
> On Wed, Nov 06, 2019 at 10:07:48PM +0800, Chuanhong Guo wrote:
> > update register descriptions and add an example binding using it.
> >
> > Signed-off-by: Chuanhong Guo <gch981213@...il.com>
> > ---
> > .../devicetree/bindings/mtd/mtk-quadspi.txt | 21 ++++++++++++++++++-
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> > index a12e3b5c495d..4860f6e96f5a 100644
> > --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> > +++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> > @@ -12,7 +12,10 @@ Required properties:
> > "mediatek,mt7623-nor", "mediatek,mt8173-nor"
> > "mediatek,mt7629-nor", "mediatek,mt8173-nor"
> > "mediatek,mt8173-nor"
> > -- reg: physical base address and length of the controller's register
> > +- reg: Contains one or two entries, each of which is a tuple consisting of a
> > + physical address and length. The first entry is the address and length
> > + of the controller register set. The optional second entry is the address
> > + and length of the area where the nor flash is mapped to.
>
> All the compatibles support 2 entries? If not, which ones?
It should be. I implemented it as an optional feature only because I
don't know the mapped address space for all these chips and can't
update every device trees.
Regards,
Chuanhong Guo
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