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Message-ID: <20191107150431.GC4114@hirez.programming.kicks-ass.net>
Date: Thu, 7 Nov 2019 16:04:31 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Ganapatrao Kulkarni <gklkml16@...il.com>
Cc: Mark Rutland <mark.rutland@....com>,
Ganapatrao Prabhakerrao Kulkarni <gkulkarni@...vell.com>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"mingo@...hat.com" <mingo@...hat.com>,
"will@...nel.org" <will@...nel.org>,
"corbet@....net" <corbet@....net>
Subject: Re: [PATCH 1/2] perf/core: Adding capability to disable PMUs event
multiplexing
On Wed, Nov 06, 2019 at 03:28:46PM -0800, Ganapatrao Kulkarni wrote:
> Issue happens when the add and del are called too many times as seen
> with 6 event case.
> The PMU hardware control registers are programmed when add and del
> functions are called.
> For pmu->read no issues since no h/w issue with the data path.
>
> Please suggest me, how can we fix this in back-end PMU driver without
> any perf core help?
As Mark already said, a (much) better description of the actual hardware
fail is required, but one possible solution would be to add a busy spin
delay when writing to the hardware registers.
Something like:
u64 now, ts = this_cpu_read(tx2_throttle);
while ((now = cycle_counter()) <= ts)
cpu_relax();
write_register(...);
this_cpu_write(tx2_throttle, now + delay_ns);
Other known tricks include reading the register back until it contains
what you just wrote to it.
But really, first properly describe how your hardware is buggered.
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