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Message-ID: <CAJs_Fx5trp2B7uOMTFZNUsYoKrO1-MWsNECKp-hz+1qCOCeU8A@mail.gmail.com>
Date: Fri, 8 Nov 2019 08:54:23 -0800
From: Rob Clark <robdclark@...omium.org>
To: Stephen Boyd <sboyd@...nel.org>
Cc: Matthias Kaehlcke <mka@...omium.org>,
Taniya Das <tdas@...eaurora.org>,
Michael Turquette <mturquette@...libre.com>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
linux-soc@...r.kernel.org, linux-clk@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>, devicetree@...r.kernel.org,
robh@...nel.org, Rob Herring <robh+dt@...nel.org>,
Jordan Crouse <jcrouse@...eaurora.org>,
Jeykumar Sankaran <jsanka@...eaurora.org>,
Sean Paul <seanpaul@...omium.org>
Subject: Re: [PATCH v4 5/5] clk: qcom: Add Global Clock controller (GCC)
driver for SC7180
On Thu, Nov 7, 2019 at 10:35 PM Stephen Boyd <sboyd@...nel.org> wrote:
>
> Quoting Rob Clark (2019-11-07 18:06:19)
> > On Thu, Nov 7, 2019 at 1:06 PM Stephen Boyd <sboyd@...nel.org> wrote:
> > >
> > > Quoting Matthias Kaehlcke (2019-10-31 10:41:49)
> > > > Hi Taniya,
> > > >
> > > > On Thu, Oct 31, 2019 at 04:59:26PM +0530, Taniya Das wrote:
> > > > > Hi Matthias,
> > > > >
> > > > > Thanks for your comments.
> > > > >
> > > > > On 10/29/2019 11:29 PM, Matthias Kaehlcke wrote:
> > > > > > Hi Taniya,
> > > > > >
> > > > > > On Mon, Oct 14, 2019 at 03:53:08PM +0530, Taniya Das wrote:
> > > > > > > Add support for the global clock controller found on SC7180
> > > > > > > based devices. This should allow most non-multimedia device
> > > > > > > drivers to probe and control their clocks.
> > > > > > >
> > > > > > > Signed-off-by: Taniya Das <tdas@...eaurora.org>
> > > > >
> > > > > >
> > > > > > v3 also had
> > > > > >
> > > > > > + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
> > > > > >
> > > > > > Removing it makes the dpu_mdss driver unhappy:
> > > > > >
> > > > > > [ 2.999855] dpu_mdss_enable+0x2c/0x58->msm_dss_enable_clk: 'iface' is not available
> > > > > >
> > > > > > because:
> > > > > >
> > > > > > mdss: mdss@...0000 {
> > > > > > ...
> > > > > >
> > > > > > => clocks = <&gcc GCC_DISP_AHB_CLK>,
> > > > > > <&gcc GCC_DISP_HF_AXI_CLK>,
> > > > > > <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > > > > > clock-names = "iface", "gcc_bus", "core";
> > > > > > };
> > > > > >
> > > > >
> > > > > The basic idea as you mentioned below was to move the CRITICAL clocks to
> > > > > probe. The clock provider to return NULL in case the clocks are not
> > > > > registered.
> > > > > This was discussed with Stephen on v3. Thus I submitted the below patch.
> > > > > clk: qcom: common: Return NULL from clk_hw OF provider.
> > > >
> > > > I see. My assumption was that the entire clock hierarchy should be registered,
> > > > but Stephen almost certainly knows better :)
> > > >
> > > > > Yes it would throw these warnings, but no functional issue is observed from
> > > > > display. I have tested it on the cheza board.
> > > >
> > > > The driver considers it an error (uses DEV_ERR to log the message) and doesn't
> > > > handle other clocks when one is found missing. I'm not really famililar with
> > > > the dpu_mdss driver, but I imagine this can have some side effects. Added some
> > > > of the authors/contributors to cc.
> > >
> > > NULL is a valid clk pointer returned by clk_get(). What is the display
> > > driver doing that makes it consider NULL an error?
> > >
> >
> > do we not have an iface clk? I think the driver assumes we should
> > have one, rather than it being an optional thing.. we could ofc change
> > that
>
> I think some sort of AHB clk is always enabled so the plan is to just
> hand back NULL to the caller when they call clk_get() on it and nobody
> should be the wiser when calling clk APIs with a NULL iface clk. The
> common clk APIs typically just return 0 and move along. Of course, we'll
> also turn the clk on in the clk driver so that hardware can function
> properly, but we don't need to expose it as a clk object and all that
> stuff if we're literally just slamming a bit somewhere and never looking
> back.
>
> But it sounds like we can't return NULL for this clk for some reason? I
> haven't tried to track it down yet but I think Matthias has found it
> causes some sort of problem in the display driver.
>
ok, I guess we can change the dpu code to allow NULL.. but what would
the return be, for example on a different SoC where we do have an
iface clk, but the clk driver isn't enabled? Would that also return
NULL? I guess it would be nice to differentiate between those cases..
BR,
-R
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