[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20191113221530.5CAD9206E3@mail.kernel.org>
Date: Wed, 13 Nov 2019 14:15:28 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Chunyan Zhang <chunyan.zhang@...soc.com>,
Mark Rutland <mark.rutland@....com>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Orson Zhai <orsonzhai@...il.com>,
Baolin Wang <baolin.wang7@...il.com>,
Chunyan Zhang <zhang.lyra@...il.com>,
Xiaolong Zhang <xiaolong.zhang@...soc.com>,
Chunyan Zhang <chunyan.zhang@...soc.com>
Subject: Re: [PATCH 1/5] clk: sprd: add gate for pll clocks
Quoting Chunyan Zhang (2019-10-25 04:13:34)
> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c
> index f59d1936b412..d8b480f852f3 100644
> --- a/drivers/clk/sprd/gate.c
> +++ b/drivers/clk/sprd/gate.c
> @@ -109,3 +120,11 @@ const struct clk_ops sprd_sc_gate_ops = {
> };
> EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
>
> +#define sprd_pll_sc_gate_unprepare sprd_sc_gate_disable
Why is there a redefine? Just use the function where it is.
> +
> +const struct clk_ops sprd_pll_sc_gate_ops = {
> + .unprepare = sprd_pll_sc_gate_unprepare,
> + .prepare = sprd_pll_sc_gate_prepare,
> + .is_enabled = sprd_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
> index dc352ea55e1f..598ce607ca0a 100644
> --- a/drivers/clk/sprd/gate.h
> +++ b/drivers/clk/sprd/gate.h
> @@ -14,16 +14,19 @@ struct sprd_gate {
> u32 enable_mask;
> u16 flags;
> u16 sc_offset;
> + u32 udelay;
Does the delay need to be 32 bits wide? Maybe a u8 or u16 will work?
Otherwise, make it an unsigned long please because the bit width doesn't
matter.
Powered by blists - more mailing lists