linux-kernel - Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

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Message-Id: <20191113230303.726AE206E3@mail.kernel.org>
Date:   Wed, 13 Nov 2019 15:03:01 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Dmitry Osipenko <digetx@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>
Cc:     linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

Quoting Dmitry Osipenko (2019-10-29 17:48:13)
> UART clock is divided using divisor values from DLM/DLL registers when
> enable-bit is unset in clk register and clk's divider configuration isn't
> taken onto account in this case. This doesn't cause any problems, but
> let's add a check for the divider's enable-bit state, for consistency.
> 
> Acked-by: Peter De Schrijver <pdeschrijver@...dia.com>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---

Is this going to be picked up or should I just apply atop the tegra PR?